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From: Mike Frysinger on 6 May 2010 15:30
On Thu, May 6, 2010 at 15:15, Anton Vorontsov wrote:
> [3] http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=5148

i doubt you feel like resending, but this is a better link:
http://blackfin.uclinux.org/gf/tracker/5148
-mike
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From: Alan Stern on 6 May 2010 16:00
On Thu, 6 May 2010, Anton Vorontsov wrote:

> It appears that the 'pehcd' driver checks the X bit only if the
> transaction is halted, otherwise the error is so far
> insignificant.
>
> I didn't find where exactly ISP1760 spec mandates 'H && X'
> handling (maybe it's in the EHCI spec?),

Yes, it is described implicitly in the EHCI spec, section 4.10.3.
Transaction errors cause the status field to be updated to reflect the
type of error, but the transaction continues to be retried until the
Active bit is set to 0. When the error counter reaches 0, the Halt bit
is set and the Active bit is cleared.

Alan Stern

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From: Sebastian Andrzej Siewior on 7 May 2010 04:10
Anton Vorontsov wrote:

> Signed-off-by: Anton Vorontsov <avorontsov(a)mvista.com>

Goodie, thanks.

Sebastian
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