Ultra low frequency VCO
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From: whit3rd on 6 Jul 2010 19:43 On Jul 6, 9:52 am, Tim Wescott <t...(a)seemywebsite.com> wrote: > > I am trying to design a PLL for very low frequencies, e.g., power line > > grid. > > I am concerned with the VCO as it is a crucial sub-circuit. I am > > aiming for > > a phase noise of approximately -100 dBc/Hz > I think that those specs would be difficult to achieve with an > all-analog oscillator running at 60Hz. Not impossible -- I could do it, An LC type oscillator is good for phase stability (multivibrator types are less good), but C values of voltage-variable capacitors are inconvenient for this range. So, you're stuck with an increductor. This is an inductor with a semi-saturating core, using a high impedance winding with DC current in it to move the inductance. It's an old technique (usually nowadays this kind of thing is only used for flux-gate magnetometers) but a goodie. Switched-capacitor filters with a 100x clock are another approach. I think the MF10 app note has an example (figure 7). <http://www.national.com/an/AN/AN-307.pdf> The fast clock can be a relatively unstable CD4046 type of VCO, it'll all average out. Hopefully.
From: JosephKK on 7 Jul 2010 07:52 On Tue, 6 Jul 2010 09:10:25 -0700 (PDT), Daku <dakupoto(a)gmail.com> wrote: >On Jul 5, 8:59 pm, Tim Wescott <t...(a)seemywebsite.com> wrote: >> I'd hardly call 60Hz "ultra low frequency". But it is pretty darned low. >> >> All the suggestions you've gotten so far are good as far as they go and >> may well be perfect -- but what are you trying to do? Do you need sine >> wave out or square? If sine wave, how pure? Do you have any >> specifications on jitter, phase noise, or frequency accuracy? >I am trying to design a PLL for very low frequencies, e.g., power line >grid. >I am concerned with the VCO as it is a crucial sub-circuit. I am >aiming for >a phase noise of approximately -100 dBc/Hz but not very sure of the >offset Yikes, it would take years (decades) to measure that. Your reference standard to measure against would be problematic as well. One cycle (about 16.667 ms) * 10^10 is over 46,000 hours, 275 weeks, 5.2 years. How about reframing it as a jitter and wander specification? >frequency. Ideally, I would like to have frequency accuracy of 1 - 5% >at most. You would blow the phase noise spec by being off by fractional millihertz. >Also, I am aware that S-parameter methods are not appropriate at these >low >frequencies. > >> >> You could digitally synthesize a 60Hz sine wave with a smallish >> processor -- I believe there are some TMS430 parts that could do it all >> in one package with a PWM output to be filtered by a simple RC. >> >> But "best" depends heavily on what you want. >> >> -- >> >> Tim Wescott >> Wescott Design Serviceshttp://www.wescottdesign.com >> >> Do you need to implement control loops in software? >> "Applied Control Theory for Embedded Systems" was written for you. >> See details athttp://www.wescottdesign.com/actfes/actfes.html
From: Tim Wescott on 7 Jul 2010 11:42 On 07/07/2010 04:52 AM, JosephKK wrote: > On Tue, 6 Jul 2010 09:10:25 -0700 (PDT), Daku<dakupoto(a)gmail.com> wrote: > >> On Jul 5, 8:59 pm, Tim Wescott<t...(a)seemywebsite.com> wrote: >>> I'd hardly call 60Hz "ultra low frequency". But it is pretty darned low. >>> >>> All the suggestions you've gotten so far are good as far as they go and >>> may well be perfect -- but what are you trying to do? Do you need sine >>> wave out or square? If sine wave, how pure? Do you have any >>> specifications on jitter, phase noise, or frequency accuracy? >> I am trying to design a PLL for very low frequencies, e.g., power line >> grid. >> I am concerned with the VCO as it is a crucial sub-circuit. I am >> aiming for >> a phase noise of approximately -100 dBc/Hz but not very sure of the >> offset > > Yikes, it would take years (decades) to measure that. Your reference > standard to measure against would be problematic as well. One cycle > (about 16.667 ms) * 10^10 is over 46,000 hours, 275 weeks, 5.2 years. Not if you multiplied the VCO output by a quadrature sine wave and looked at the noise of the result. Then it would just take minutes. > How about reframing it as a jitter and wander specification? > >> frequency. Ideally, I would like to have frequency accuracy of 1 - 5% >> at most. > > You would blow the phase noise spec by being off by fractional > millihertz. I think the OP's idea is that the absolute frequency vs. command voltage can have an offset, because the PLL will be correcting for it. It's the random contribution to phase noise that he's trying to limit. It's an awfully tight spec -- and one that could easily get blown with one noisy stage in the chain, outside of the oscillator -- but I don't think it's impossible to do on a bench top. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html
From: j on 7 Jul 2010 11:43 Phase noise and frequency accuracy are two different parameters. For example its possible to have a phase noise spec of great than 100 dbs at x number of hz of the carrier and have over 10KHz or more of frequency in accuracy. Jitter is the parameter that has a direct correlation to phase noise. Is the goal of the project to lock to 60 Hz line,(it's the ref for the loop), and provide a clean 60 Hz out? j
From: JosephKK on 7 Jul 2010 23:04
On Wed, 07 Jul 2010 08:42:15 -0700, Tim Wescott <tim(a)seemywebsite.com> wrote: >On 07/07/2010 04:52 AM, JosephKK wrote: >> On Tue, 6 Jul 2010 09:10:25 -0700 (PDT), Daku<dakupoto(a)gmail.com> wrote: >> >>> On Jul 5, 8:59 pm, Tim Wescott<t...(a)seemywebsite.com> wrote: >>>> I'd hardly call 60Hz "ultra low frequency". But it is pretty darned low. >>>> >>>> All the suggestions you've gotten so far are good as far as they go and >>>> may well be perfect -- but what are you trying to do? Do you need sine >>>> wave out or square? If sine wave, how pure? Do you have any >>>> specifications on jitter, phase noise, or frequency accuracy? >>> I am trying to design a PLL for very low frequencies, e.g., power line >>> grid. >>> I am concerned with the VCO as it is a crucial sub-circuit. I am >>> aiming for >>> a phase noise of approximately -100 dBc/Hz but not very sure of the >>> offset >> >> Yikes, it would take years (decades) to measure that. Your reference >> standard to measure against would be problematic as well. One cycle >> (about 16.667 ms) * 10^10 is over 46,000 hours, 275 weeks, 5.2 years. > >Not if you multiplied the VCO output by a quadrature sine wave and >looked at the noise of the result. Then it would just take minutes. What is done at RF of 60 MHz, 600 MHz, or 6 GHz to make the measurement easier, does not make it faster. Sure, it takes a second or so at 600 MHz for 100 dBc. And a megasecond or so at 60 Hz to measure it in the RF traditional way. Simple scaling. That is why i recommended changing to jitter and wander specifications, which you have a decent shot at measuring in an hour or so. Or maybe you are on to something, but for my and OPs sake, please flesh it out a lot more, with some calcs please. > >> How about reframing it as a jitter and wander specification? >> >>> frequency. Ideally, I would like to have frequency accuracy of 1 - 5% >>> at most. >> >> You would blow the phase noise spec by being off by fractional >> millihertz. > >I think the OP's idea is that the absolute frequency vs. command voltage >can have an offset, because the PLL will be correcting for it. It's the >random contribution to phase noise that he's trying to limit. > >It's an awfully tight spec -- and one that could easily get blown with >one noisy stage in the chain, outside of the oscillator -- but I don't >think it's impossible to do on a bench top. |