When is a fractional-N PLL needed?
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From: gretzteam on 4 Aug 2010 13:23 Hi, I'm trying to understand when a fractional-N PLL is required. I'm doing this in an FPGA so it's an ADPLL, but I think my questions are basic enough that it applies to any PLL. When using a basic PLL topology: ref -> PFD -> LPF -> NCO -> output | | |<-------div-N<------| I can only create output clocks that are at an integer multiple of the reference input. For example, if ref=10kHz, I can create 20, 30, 40... Say I would like to be able to generate 52kHz. I see two ways: 1) Keep the exact same topology, but add a div-M at the output of the system. This way, I could set div-N=52, making the output 520kHz, and div-M=10, essentially getting my back to 52kHz. However, even for trivial output clock value, the N divider can get quite high which makes the whole thing harder to design. 2) Have the div-N value change between 5 and 6 in a way that it's 5.2 on average (probably a sigma-delta modulator would control this). This doesn't seem to have the disadvantage of option 1, but opens-up a whole new level of difficulty with the sigma-delta modulator etc... Am I understanding the trade-offs correctly, or I'm way out in left field? Thanks!
From: Steve Pope on 4 Aug 2010 13:30 gretzteam <gretzteam(a)n_o_s_p_a_m.yahoo.com> wrote: >I'm trying to understand when a fractional-N PLL is required. For some sets of design constraints, the fractional-N approach leads to lower phase noise than non-fractional-N approaches. This is (probably) the main reason it is used. S.
From: Tim Wescott on 4 Aug 2010 15:14 On 08/04/2010 10:23 AM, gretzteam wrote: > Hi, > I'm trying to understand when a fractional-N PLL is required. I'm doing > this in an FPGA so it's an ADPLL, but I think my questions are basic enough > that it applies to any PLL. > > When using a basic PLL topology: > > ref -> PFD -> LPF -> NCO -> output > | | > |<-------div-N<------| > > I can only create output clocks that are at an integer multiple of the > reference input. For example, if ref=10kHz, I can create 20, 30, 40... > > Say I would like to be able to generate 52kHz. I see two ways: > > 1) Keep the exact same topology, but add a div-M at the output of the > system. This way, I could set div-N=52, making the output 520kHz, and > div-M=10, essentially getting my back to 52kHz. However, even for trivial > output clock value, the N divider can get quite high which makes the whole > thing harder to design. > > 2) Have the div-N value change between 5 and 6 in a way that it's 5.2 on > average (probably a sigma-delta modulator would control this). This doesn't > seem to have the disadvantage of option 1, but opens-up a whole new level > of difficulty with the sigma-delta modulator etc... > > Am I understanding the trade-offs correctly, or I'm way out in left field? 3) lower the reference frequency to 2kHz (or raise it to 13kHz for your specific example). Touching on Steve's comment, for some synthesizers you can get lower phase noise with the fractional-N division (and proper filtering of the phase error) than you can by lowering the reference frequency (which is one other option). -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html
From: Allan Herriman on 4 Aug 2010 19:19 On Wed, 04 Aug 2010 12:23:24 -0500, gretzteam wrote: > Hi, > I'm trying to understand when a fractional-N PLL is required. I'm doing > this in an FPGA so it's an ADPLL, but I think my questions are basic > enough that it applies to any PLL. > > When using a basic PLL topology: > > ref -> PFD -> LPF -> NCO -> output > | | > |<-------div-N<------| > > I can only create output clocks that are at an integer multiple of the > reference input. For example, if ref=10kHz, I can create 20, 30, 40... > > Say I would like to be able to generate 52kHz. I see two ways: > > 1) Keep the exact same topology, but add a div-M at the output of the > system. This way, I could set div-N=52, making the output 520kHz, and > div-M=10, essentially getting my back to 52kHz. However, even for > trivial output clock value, the N divider can get quite high which makes > the whole thing harder to design. Dividers are easy to design and cheap to implement. The real problem is that the PFD frequency is lower, which leads to (usually) undesirable tradeoffs with the loop filter, phase noise, reference spurs, etc. > 2) Have the div-N value change between 5 and 6 in a way that it's 5.2 on > average (probably a sigma-delta modulator would control this). This > doesn't seem to have the disadvantage of option 1, but opens-up a whole > new level of difficulty with the sigma-delta modulator etc... Again, these aren't too hard to design, and usually worth the effort. > Am I understanding the trade-offs correctly, or I'm way out in left > field? You seem to be on the right track. I present the following alternative (and less practical) methods for interest. Approach #2b: Use another NCO for the feedback divider. This produces an average division of 5.2, but unlike the sigma-delta modulator, the phase modulation produced is deterministic. The output spectrum will have strong spurs (as opposed to the continuous noisy spectrum produced by the sigma delta one). I have seen (analog) PLLs attempt to estimate this effect and inject a saw tooth shaped current into the PFD output to cancel it. About 20dB spur reduction can be achieved - this is limited by the accuracy and frequency response of the DACs employed. I don't know whether this is used in contemporary parts, but it is an interesting technique nonetheless. I believe chip designers stopped doing this when they figured out how to design sigma delta modulators. Approach #3: Use a mixer to translate the output frequency by some offset. This is easy to do if the signals are sinusoidal (in which case the mixer is just a complex multiplier) but a little difficult if they are square waves (which I guess would be commonly used inside a DPLL). The mixer is placed between the output and the feedback divider. Example: Divide the 10kHz down to 2kHz, and generate a sinewave at this frequency. Use it to mix the 52kHz PLL output down to 50kHz, then put that into the feedback divider, which produces the 10kHz that goes into the PFD. I've never seen that approach used in a DPLL (particularly one in an FPGA). Approach #4: Use a VCO at a frequency much higher than you need, then divide it down to the frequency you want. (Again, this isn't applicable for a DPLL inside an FPGA.) There are plenty of cheap analog frequency synthesiser chips available that have ring-oscillator VCOs that operate in the range 1-2GHz. They usually have the dividers you need on-chip as well. You'll need to use one that allows the use of an external loop filter, as the on- chip loop filters usually result in bws of some MHz and your reference is only 10kHz. Cheers, Allan
From: Allan Herriman on 4 Aug 2010 19:25
On Wed, 04 Aug 2010 23:19:21 +0000, Allan Herriman wrote: > On Wed, 04 Aug 2010 12:23:24 -0500, gretzteam wrote: > >> Hi, >> I'm trying to understand when a fractional-N PLL is required. I'm doing >> this in an FPGA so it's an ADPLL, but I think my questions are basic >> enough that it applies to any PLL. >> >> When using a basic PLL topology: >> >> ref -> PFD -> LPF -> NCO -> output >> | | >> |<-------div-N<------| >> >> I can only create output clocks that are at an integer multiple of the >> reference input. For example, if ref=10kHz, I can create 20, 30, 40... >> >> Say I would like to be able to generate 52kHz. I see two ways: >> >> 1) Keep the exact same topology, but add a div-M at the output of the >> system. This way, I could set div-N=52, making the output 520kHz, and >> div-M=10, essentially getting my back to 52kHz. However, even for >> trivial output clock value, the N divider can get quite high which >> makes the whole thing harder to design. > > Dividers are easy to design and cheap to implement. The real problem is > that the PFD frequency is lower, which leads to (usually) undesirable > tradeoffs with the loop filter, phase noise, reference spurs, etc. Oops, I see I missed something there. (I thought you were talking about a divider on the reference input rather than the NCO output.) I hope you found the rest of the post entertaining though. > > Cheers, > Allan |