battery chargers, again
in [Design]
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From: JosephKK on 3 Oct 2009 09:49 On Mon, 28 Sep 2009 18:40:55 -0700, Jim Thompson <To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >On Tue, 29 Sep 2009 09:24:13 +0800, who where <noone(a)home.net> wrote: > >>On Mon, 28 Sep 2009 15:43:21 -0700, Joerg <invalid(a)invalid.invalid> >>wrote: >> >> >>>The same happened to me after dusk on the road from Durness to Inverness >>>in Scotland. The old Ford Cortina just stopped, no more electric. Looked >>>around, opened fuse box, the big one was gone. "Oh s..t!" ... no other >>>cars traveling that road at this late hour. I did meet one horse though, >>>alone, just wandering about (you see those a lot there). I seriously >>>doubt it would have agreed to carry me to Inverness. So I slowly walked >>>back and lucked out, found the fuse in the dirt. It had simply fallen out. >> >>Lucas, Prince of Darkness? > >Sno-o-o-o-ort! Damn! Chardonnay up the nose :-( > > ...Jim Thompson Congratulations, now you know in the fullest way why i have this group marked as not safe to read with a mouthful.
From: Joerg on 3 Oct 2009 15:04 John Larkin wrote: > On Fri, 02 Oct 2009 07:09:34 -0700, Joerg <invalid(a)invalid.invalid> > wrote: > >> John Larkin wrote: >>> On Thu, 01 Oct 2009 14:06:36 -0700, Joerg <invalid(a)invalid.invalid> >>> wrote: >>> >>> >>>>> The layout is tedious, because we're optimizing the BGA FPGA routing >>>>> as we go along... can't just draw the schematic and go forward to the >>>>> board. >>>>> >>>> Ouch. >>>> >>>> >>>>> This *is* rev 30. >>>>> >>>> Double-Ouch. I am firing up rev 1 of a really unorthodox cicuit this >>>> afternoon. Wish me luck, and if you hear a muffled boom north-east from >>>> you guys ... >>> Was that an earthquake or was the Joerg? >>> >> No, it worked, must have been an earthquake then ;-) >> >> >>> To calarify, this is rev 30 of the working layout. We haven't fabbed >>> any boards yet. >>> >>> The PCB file will be formally released as 26D150A.PCB, to make rev A >>> of the product. During layout, we number every iteration. If we change >>> a net or add a resistor or whatever, we start with schematic >>> 26S150A29.SCH, change it to 26S150A30.SCH and save that, make the >>> differences file ECO30, apply that onto pcb 26D150A29.PCB, and save as >>> 26D150A30.PCB. So we have all the iterations and all the ECO files, >>> all organized. When we release the schematic and pcb as rev A, we >>> delete all that working junk. Since we're iterating on the BGA pinout, >>> we're spinning a lot of ECOs. >>> >>> If we go A to B, we start the sequence all over, 26S150B1.SCH etc. >>> >> I do it similarly, except adding X1, X2 and so on. And I usually cannot >> erase the intermediates upon ECO-release because federal agencies often >> require that a complete design history be kept. So if you do medical, >> maybe better not to toss it. > > The next logical step would be to log every key and mouse click, and > videotape everything that happens in Engineering. > Orwell ... But seriously, all they want is that you are able to show, for example, why you dismissed a direct conversions scheme somewhere, how the old schematic looked, and how the new one looks. An answer like "Oh, ahm, well, I guess we must have purged the old files" raises some flags and creates an urge to dig some more. They don't want to know the shoe size of all the people signing an ECO. At least not yet :-) -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.
From: John Larkin on 4 Oct 2009 17:44 On Sat, 03 Oct 2009 12:04:03 -0700, Joerg <invalid(a)invalid.invalid> wrote: >John Larkin wrote: >> On Fri, 02 Oct 2009 07:09:34 -0700, Joerg <invalid(a)invalid.invalid> >> wrote: >> >>> John Larkin wrote: >>>> On Thu, 01 Oct 2009 14:06:36 -0700, Joerg <invalid(a)invalid.invalid> >>>> wrote: >>>> >>>> >>>>>> The layout is tedious, because we're optimizing the BGA FPGA routing >>>>>> as we go along... can't just draw the schematic and go forward to the >>>>>> board. >>>>>> >>>>> Ouch. >>>>> >>>>> >>>>>> This *is* rev 30. >>>>>> >>>>> Double-Ouch. I am firing up rev 1 of a really unorthodox cicuit this >>>>> afternoon. Wish me luck, and if you hear a muffled boom north-east from >>>>> you guys ... >>>> Was that an earthquake or was the Joerg? >>>> >>> No, it worked, must have been an earthquake then ;-) >>> >>> >>>> To calarify, this is rev 30 of the working layout. We haven't fabbed >>>> any boards yet. >>>> >>>> The PCB file will be formally released as 26D150A.PCB, to make rev A >>>> of the product. During layout, we number every iteration. If we change >>>> a net or add a resistor or whatever, we start with schematic >>>> 26S150A29.SCH, change it to 26S150A30.SCH and save that, make the >>>> differences file ECO30, apply that onto pcb 26D150A29.PCB, and save as >>>> 26D150A30.PCB. So we have all the iterations and all the ECO files, >>>> all organized. When we release the schematic and pcb as rev A, we >>>> delete all that working junk. Since we're iterating on the BGA pinout, >>>> we're spinning a lot of ECOs. >>>> >>>> If we go A to B, we start the sequence all over, 26S150B1.SCH etc. >>>> >>> I do it similarly, except adding X1, X2 and so on. And I usually cannot >>> erase the intermediates upon ECO-release because federal agencies often >>> require that a complete design history be kept. So if you do medical, >>> maybe better not to toss it. >> >> The next logical step would be to log every key and mouse click, and >> videotape everything that happens in Engineering. >> > >Orwell ... > >But seriously, all they want is that you are able to show, for example, >why you dismissed a direct conversions scheme somewhere, how the old >schematic looked, and how the new one looks. An answer like "Oh, ahm, >well, I guess we must have purged the old files" raises some flags and >creates an urge to dig some more. > >They don't want to know the shoe size of all the people signing an ECO. >At least not yet :-) The ECOs I'm talking about are just "differences" files that PADS makes whenever you edit a schematic and want to carry the changes over to the PCB. We can do several of them a day when a board is being created or revised. At the end, we crosscheck the schematic and pcb netlists and formally release the new letter rev. We always archive all the released files of all the revs, and anything else that controls the configuration or processing of anything shippable. We do formally release "real" ECOs. But so far, we answer to nobody as regards internal procedures. What you buy is what you get. John
From: Joerg on 4 Oct 2009 18:01 John Larkin wrote: > On Sat, 03 Oct 2009 12:04:03 -0700, Joerg <invalid(a)invalid.invalid> > wrote: > >> John Larkin wrote: >>> On Fri, 02 Oct 2009 07:09:34 -0700, Joerg <invalid(a)invalid.invalid> >>> wrote: >>> >>>> John Larkin wrote: [...] >>>>> To calarify, this is rev 30 of the working layout. We haven't fabbed >>>>> any boards yet. >>>>> >>>>> The PCB file will be formally released as 26D150A.PCB, to make rev A >>>>> of the product. During layout, we number every iteration. If we change >>>>> a net or add a resistor or whatever, we start with schematic >>>>> 26S150A29.SCH, change it to 26S150A30.SCH and save that, make the >>>>> differences file ECO30, apply that onto pcb 26D150A29.PCB, and save as >>>>> 26D150A30.PCB. So we have all the iterations and all the ECO files, >>>>> all organized. When we release the schematic and pcb as rev A, we >>>>> delete all that working junk. Since we're iterating on the BGA pinout, >>>>> we're spinning a lot of ECOs. >>>>> >>>>> If we go A to B, we start the sequence all over, 26S150B1.SCH etc. >>>>> >>>> I do it similarly, except adding X1, X2 and so on. And I usually cannot >>>> erase the intermediates upon ECO-release because federal agencies often >>>> require that a complete design history be kept. So if you do medical, >>>> maybe better not to toss it. >>> The next logical step would be to log every key and mouse click, and >>> videotape everything that happens in Engineering. >>> >> Orwell ... >> >> But seriously, all they want is that you are able to show, for example, >> why you dismissed a direct conversions scheme somewhere, how the old >> schematic looked, and how the new one looks. An answer like "Oh, ahm, >> well, I guess we must have purged the old files" raises some flags and >> creates an urge to dig some more. >> >> They don't want to know the shoe size of all the people signing an ECO. >> At least not yet :-) > > The ECOs I'm talking about are just "differences" files that PADS > makes whenever you edit a schematic and want to carry the changes over > to the PCB. We can do several of them a day when a board is being > created or revised. At the end, we crosscheck the schematic and pcb > netlists and formally release the new letter rev. We always archive > all the released files of all the revs, and anything else that > controls the configuration or processing of anything shippable. > That appears to be a sound procedure. As long as some prose is kept alongside so you don't have to wonder in front of an inspector "Now why did we change that?". > We do formally release "real" ECOs. > > But so far, we answer to nobody as regards internal procedures. What > you buy is what you get. > Can't do that in many of my fields because they are heavily regulated. Aero (stuff that will actually be flown for decades) and medical have their strict rules. In fact, I know of one large medical device manufacturer where the FDA put the padlocks on the doors. Very embarrassing. Luckily not a client :-) -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.
From: krw on 4 Oct 2009 18:06
On Sun, 04 Oct 2009 14:44:45 -0700, John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >On Sat, 03 Oct 2009 12:04:03 -0700, Joerg <invalid(a)invalid.invalid> >wrote: > >>John Larkin wrote: >>> On Fri, 02 Oct 2009 07:09:34 -0700, Joerg <invalid(a)invalid.invalid> >>> wrote: >>> >>>> John Larkin wrote: >>>>> On Thu, 01 Oct 2009 14:06:36 -0700, Joerg <invalid(a)invalid.invalid> >>>>> wrote: >>>>> >>>>> >>>>>>> The layout is tedious, because we're optimizing the BGA FPGA routing >>>>>>> as we go along... can't just draw the schematic and go forward to the >>>>>>> board. >>>>>>> >>>>>> Ouch. >>>>>> >>>>>> >>>>>>> This *is* rev 30. >>>>>>> >>>>>> Double-Ouch. I am firing up rev 1 of a really unorthodox cicuit this >>>>>> afternoon. Wish me luck, and if you hear a muffled boom north-east from >>>>>> you guys ... >>>>> Was that an earthquake or was the Joerg? >>>>> >>>> No, it worked, must have been an earthquake then ;-) >>>> >>>> >>>>> To calarify, this is rev 30 of the working layout. We haven't fabbed >>>>> any boards yet. >>>>> >>>>> The PCB file will be formally released as 26D150A.PCB, to make rev A >>>>> of the product. During layout, we number every iteration. If we change >>>>> a net or add a resistor or whatever, we start with schematic >>>>> 26S150A29.SCH, change it to 26S150A30.SCH and save that, make the >>>>> differences file ECO30, apply that onto pcb 26D150A29.PCB, and save as >>>>> 26D150A30.PCB. So we have all the iterations and all the ECO files, >>>>> all organized. When we release the schematic and pcb as rev A, we >>>>> delete all that working junk. Since we're iterating on the BGA pinout, >>>>> we're spinning a lot of ECOs. >>>>> >>>>> If we go A to B, we start the sequence all over, 26S150B1.SCH etc. >>>>> >>>> I do it similarly, except adding X1, X2 and so on. And I usually cannot >>>> erase the intermediates upon ECO-release because federal agencies often >>>> require that a complete design history be kept. So if you do medical, >>>> maybe better not to toss it. >>> >>> The next logical step would be to log every key and mouse click, and >>> videotape everything that happens in Engineering. >>> >> >>Orwell ... >> >>But seriously, all they want is that you are able to show, for example, >>why you dismissed a direct conversions scheme somewhere, how the old >>schematic looked, and how the new one looks. An answer like "Oh, ahm, >>well, I guess we must have purged the old files" raises some flags and >>creates an urge to dig some more. >> >>They don't want to know the shoe size of all the people signing an ECO. >>At least not yet :-) > >The ECOs I'm talking about are just "differences" files that PADS >makes whenever you edit a schematic and want to carry the changes over >to the PCB. We can do several of them a day when a board is being >created or revised. At the end, we crosscheck the schematic and pcb >netlists and formally release the new letter rev. We always archive >all the released files of all the revs, and anything else that >controls the configuration or processing of anything shippable. What do you do with "what if" branches off a work in progress? What does Joerg do? >We do formally release "real" ECOs. > >But so far, we answer to nobody as regards internal procedures. What >you buy is what you get. Joerg's process sounds like it's the "bury 'em in bullshit" answer to design documentation. ;-) |