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From: Candide Voltaire on 19 Mar 2010 03:03
I'm looking for a passive rc-network which produces a delay of 200ns
for a 5MHz sinusoidal voltage.
Which is the minimum number of RCs to achieve this? Are there some
schematics optimized for this purpose?


Candide
From: Grant on 19 Mar 2010 03:37
On Fri, 19 Mar 2010 00:03:33 -0700 (PDT), Candide Voltaire <candideguevara(a)gmail.com> wrote:

>I'm looking for a passive rc-network which produces a delay of 200ns
>for a 5MHz sinusoidal voltage.
>Which is the minimum number of RCs to achieve this? Are there some
>schematics optimized for this purpose?

Very funny.
From: oopere on 19 Mar 2010 04:21
Candide Voltaire wrote:
> I'm looking for a passive rc-network which produces a delay of 200ns
> for a 5MHz sinusoidal voltage.
> Which is the minimum number of RCs to achieve this? Are there some
> schematics optimized for this purpose?
>
>
> Candide

Since the required delay is a whole period, the answer is yes, there is
an optimum schematic, although it is a degenerate case of RC, with R=0,
C=0 (inexpensive)

Vin----R--�--Vout
|
C
|
gnd

Pere
From: Jan Panteltje on 19 Mar 2010 07:25
On a sunny day (Fri, 19 Mar 2010 09:21:13 +0100) it happened oopere
<me(a)somewhere.net> wrote in <hnvc5q$a5u$1(a)defalla.upc.es>:

>Candide Voltaire wrote:
>> I'm looking for a passive rc-network which produces a delay of 200ns
>> for a 5MHz sinusoidal voltage.
>> Which is the minimum number of RCs to achieve this? Are there some
>> schematics optimized for this purpose?
>>
>>
>> Candide
>
>Since the required delay is a whole period, the answer is yes, there is
>an optimum schematic, although it is a degenerate case of RC, with R=0,
>C=0 (inexpensive)
>
>Vin----R--�--Vout
> |
> C
> |
> gnd
>
>Pere

Na, C=0 and R=0 is extremely expensive.
Impossible to make even.
Better just use some meters of coax cable to delay one period :-)
From: Candide Voltaire on 19 Mar 2010 07:25
On Mar 19, 9:21 am, oopere <m...(a)somewhere.net> wrote:
> Candide Voltaire wrote:
> > I'm looking for a passive rc-network which produces a delay of 200ns
> > for a 5MHz sinusoidal voltage.
> > Which is the minimum number of RCs to achieve this? Are there some
> > schematics optimized for this purpose?
>
> > Candide
>
> Since the required delay is a whole period, the answer is yes, there is
> an optimum schematic, although it is a degenerate case of RC, with R=0,
> C=0 (inexpensive)
>
> Vin----R--·--Vout
>            |
>            C
>            |
>           gnd
>
> Pere

OK that's correct, do you also have an answer in case we want 180ns?

Candide
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