delay for hdl code generation and general concept
in [Matlab]
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From: khan Sim on 4 Jun 2010 03:34 well i have two questions related to the use of delay block in simulink model for hdl code generation. 1. is delay block synthesizable in hdl, that is if i burn the verilog code for delay on fpga, will it produce delay 2. suppose i have a signal A with 4 samples. and signal B following signal A. they are comming throgh the same wire with a constant sampling rate, that is the sample rate of A = the sample rate of B. if use a delay block, will it not effect the integrity of sample B following the sample A? if i use delay, will i not miss a sample ???? will there not be overlap of samples??? kind regards Khan
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