detecting L1 data cache line size
in [Solaris]
|
Prev: Solaris 10 x86 u8 on i5 661 Gigabyte GP-P55A
Next: solaris update8 causing SCR issues because of patch 118833-36
From: Luke Dalessandro on 14 May 2010 17:13 Is anyone aware of a cross-architecture way to detect the size of an L1 data cache line size? Linux has "getconf LEVEL1_DCACHE_LINESIZE" Mac OS has "sysctl hw.cachelinesize" All I've found is a reference to "prtconf -v", but my output doesn't include anything about caches. I can use cpuid directly on x86, but I haven't found anything sparc-ish to work yet. Thanks in advance, Luke
From: Casper H.S. Dik on 16 May 2010 07:49 Luke Dalessandro <ldalessandro(a)gmail.com> writes: >Is anyone aware of a cross-architecture way to detect the size of an >L1 data cache line size? >Linux has "getconf LEVEL1_DCACHE_LINESIZE" >Mac OS has "sysctl hw.cachelinesize" >All I've found is a reference to "prtconf -v", but my output doesn't >include anything about caches. I can use cpuid directly on x86, but I >haven't found anything sparc-ish to work yet. No entries like: name='l1-dcache-size' type=int items=1 value=00006000 name='l1-dcache-line-size' type=int items=1 value=00000040 name='l1-dcache-associativity' type=int items=1 value=00000006 name='l1-icache-size' type=int items=1 value=00008000 name='l1-icache-line-size' type=int items=1 value=00000040 name='l1-icache-associativity' type=int items=1 value=00000008 name='l2-cache-size' type=int items=1 value=00080000 name='l2-cache-line-size' type=int items=1 value=00000040 name='l2-cache-associativity' type=int items=1 value=00000008 -- Expressed in this posting are my opinions. They are in no way related to opinions held by my employer, Sun Microsystems. Statements on Sun products included here are not gospel and may be fiction rather than truth.
From: Andrew Gabriel on 16 May 2010 08:25 In article <4befdbe0$0$22916$e4fe514c(a)news.xs4all.nl>, Casper H.S. Dik <Casper.Dik(a)Sun.COM> writes: > Luke Dalessandro <ldalessandro(a)gmail.com> writes: > >>Is anyone aware of a cross-architecture way to detect the size of an >>L1 data cache line size? > >>Linux has "getconf LEVEL1_DCACHE_LINESIZE" >>Mac OS has "sysctl hw.cachelinesize" > >>All I've found is a reference to "prtconf -v", but my output doesn't >>include anything about caches. I can use cpuid directly on x86, but I >>haven't found anything sparc-ish to work yet. I believe it's generally 64 bytes as shown below, but it would be a mistake to assume that all CPUs in the system have the same cache-line-size -- sparc systems in particular have a long history of allowing use of mixtures of CPUs of different specs so if it were to change, you might find some CPUs on a system have different cache-line-size than others, and that this might change whilst the system is running. > No entries like: > > name='l1-dcache-size' type=int items=1 > value=00006000 > name='l1-dcache-line-size' type=int items=1 > value=00000040 > name='l1-dcache-associativity' type=int items=1 > value=00000006 > name='l1-icache-size' type=int items=1 > value=00008000 > name='l1-icache-line-size' type=int items=1 > value=00000040 > name='l1-icache-associativity' type=int items=1 > value=00000008 > name='l2-cache-size' type=int items=1 > value=00080000 > name='l2-cache-line-size' type=int items=1 > value=00000040 > name='l2-cache-associativity' type=int items=1 > value=00000008 -- Andrew Gabriel [email address is not usable -- followup in the newsgroup]
From: Luke Dalessandro on 16 May 2010 09:48 On May 16, 7:49 am, Casper H.S. Dik <Casper....(a)Sun.COM> wrote: > Luke Dalessandro <ldalessan...(a)gmail.com> writes: > >Is anyone aware of a cross-architecture way to detect the size of an > >L1 data cache line size? > >Linux has "getconf LEVEL1_DCACHE_LINESIZE" > >Mac OS has "sysctl hw.cachelinesize" > >All I've found is a reference to "prtconf -v", but my output doesn't > >include anything about caches. I can use cpuid directly on x86, but I > >haven't found anything sparc-ish to work yet. > > No entries like: > > name='l1-dcache-size' type=int items=1 > value=00006000 > name='l1-dcache-line-size' type=int items=1 > value=00000040 > name='l1-dcache-associativity' type=int items=1 > value=00000006 > name='l1-icache-size' type=int items=1 > value=00008000 > name='l1-icache-line-size' type=int items=1 > value=00000040 > name='l1-icache-associativity' type=int items=1 > value=00000008 > name='l2-cache-size' type=int items=1 > value=00080000 > name='l2-cache-line-size' type=int items=1 > value=00000040 > name='l2-cache-associativity' type=int items=1 > value=00000008 > Unfortunately, no. I was hoping for that, but I just get a bunch of this... cpu (driver not attached) cpu (driver not attached) cpu (driver not attached) cpu (driver not attached) cpu (driver not attached) cpu (driver not attached) cpu (driver not attached) Luke > -- > Expressed in this posting are my opinions. They are in no way related > to opinions held by my employer, Sun Microsystems. > Statements on Sun products included here are not gospel and may > be fiction rather than truth.
From: Luke Dalessandro on 16 May 2010 09:57
On May 16, 8:25 am, and...(a)cucumber.demon.co.uk (Andrew Gabriel) wrote: > In article <4befdbe0$0$22916$e4fe5...(a)news.xs4all.nl>, > Casper H.S. Dik <Casper....(a)Sun.COM> writes: > > > Luke Dalessandro <ldalessan...(a)gmail.com> writes: > > >>Is anyone aware of a cross-architecture way to detect the size of an > >>L1 data cache line size? > > >>Linux has "getconf LEVEL1_DCACHE_LINESIZE" > >>Mac OS has "sysctl hw.cachelinesize" > > >>All I've found is a reference to "prtconf -v", but my output doesn't > >>include anything about caches. I can use cpuid directly on x86, but I > >>haven't found anything sparc-ish to work yet. > > I believe it's generally 64 bytes as shown below, but it would > be a mistake to assume that all CPUs in the system have the same > cache-line-size -- sparc systems in particular have a long history > of allowing use of mixtures of CPUs of different specs so if it > were to change, you might find some CPUs on a system have different > cache-line-size than others, and that this might change whilst the > system is running. > Hmm... that's awkward. I guess I can just use 128, it just seems wrong to embed a constant into the configuration like that. Luke > > > > > > No entries like: > > > name='l1-dcache-size' type=int items=1 > > value=00006000 > > name='l1-dcache-line-size' type=int items=1 > > value=00000040 > > name='l1-dcache-associativity' type=int items=1 > > value=00000006 > > name='l1-icache-size' type=int items=1 > > value=00008000 > > name='l1-icache-line-size' type=int items=1 > > value=00000040 > > name='l1-icache-associativity' type=int items=1 > > value=00000008 > > name='l2-cache-size' type=int items=1 > > value=00080000 > > name='l2-cache-line-size' type=int items=1 > > value=00000040 > > name='l2-cache-associativity' type=int items=1 > > value=00000008 > > -- > Andrew Gabriel > [email address is not usable -- followup in the newsgroup] |