drivers/pci/intel-iommu.c: errors with smaller iommu widths
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From: Tom Lyon on 19 Apr 2010 19:00 I agree, but I defer to Mr. Woodhouse. On Monday 19 April 2010 03:43:39 pm Andrew Morton wrote: > On Mon, 19 Apr 2010 14:44:16 -0700 > "Tom Lyon" <pugs(a)cisco.com> wrote: > > > > > When using iommu_domain_alloc with the Intel iommu, the domain address width > > is always initialized to 48 bits (agaw 2). __This domain->agaw value is then > > used by pfn_to_dma_pte to (always) build a 4 level page table. __However, not > > all systems support iommu width of 48 or 4 level page tables. __In particular, > > the Core i5-660 and i5-670 support an address width of 36 bits (not 39!), an > > agaw of only 1, and only 3 level page tables. > > > > This version of the patch simply lops off extra levels of the page tables if > > the agaw value of the iommu is less than what is currently allocated for the > > domain (in intel_iommu_attach_device). If there were already allocated > > addresses above what the new iommu can handle, EFAULT is returned. > > Signed-off-by: Tom Lyon <pugs(a)cisco.com> > > This smells like a 2.6.34 patch. Do you agree? > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo(a)vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ |