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From: eruan on 25 Oct 2009 17:19
>Hi.
>
>I just saw this thread and initially didn't notice that it's aged.
>
>My experience is that the FIFORESET only works when EPxFIFOCFG is 0x00
>(manual mode). So in my code I clear it to 0x00, do the FIFORESET
>stuff, do OUTPKTEND for each buffer and eventually program EPxFIFOCFG
>to the desired value.
>
>The GP doesn't seem to do this and if he still suffers problems with
>his FX2 it might be worth trying. It would explain the reset/no-reset
>symtoms, too.
>
>Regards,
>Marc
>
>

The source of the problem is actually the DYN_OUT bit in REVCTL. All
examples given in FX2 TRM tell us to set the bits in REVCTL(REVCTL=0x03).
The DYN_out bit when set disables the auto-arming(TRM 15.5.9). But
configuration of FIFO registers require DYN_OUT to be set. The REVCTL=0x03
is actually only required before we reset the FIFO buffers. Hence the trick
is to reset the REVCTL(REVCTL=0x00) after resetting the FIFO, and
EPxFIFOCFG must be done after resetting REVCTL. Try this sequence and see
if it works.
1. IFCONFIG=??; //Your choice of configuration
2. REVCTL=0x03;
SYNCDELAY
3. Configure endpoints
EP2CFG=0xA2; //endpoint2 as outendpoint
EP6CFG=0xE2; //endpoint6 an inendpoint
4. Fifo reset
FIFORESET=0x80;
FIFORESET=0x02;
FIFORESET=0x06;
FIFORESET=0X00;
5. Prime outendpoints
OUTPKTEND=0x82;
OUTPKTEND=0x82; //2 times for double buffer
SYNCDELAY;
6. Now that fifo has been reset we can revert the REVCTL bits for autoarm
REVCTL=0x00;
SYNCDELAY;
7. Configure FIFO
EP2FIFOCFG=bmAUTOOUT; //set the commit
EP6FIFOCFG=bmAUTOIN; //you can also set WORDWIDE here
8. Set autoinlen for inendpoints
EP6AUTOINLENH=??;
EP6AUTOINLENL=??;
SYNCDELAY;
We are done. The example given above use endpoint2 as out endpoint and
endpoint6 as in endpoint. With 8 bit FIFO access.





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From: __grzegorz__ on 16 Nov 2009 09:33
>>Hi.
>>
>>I just saw this thread and initially didn't notice that it's aged.
>>
>>My experience is that the FIFORESET only works when EPxFIFOCFG is 0x00
>>(manual mode). So in my code I clear it to 0x00, do the FIFORESET
>>stuff, do OUTPKTEND for each buffer and eventually program EPxFIFOCFG
>>to the desired value.
>>
>>The GP doesn't seem to do this and if he still suffers problems with
>>his FX2 it might be worth trying. It would explain the reset/no-reset
>>symtoms, too.
>>
>>Regards,
>>Marc
>>
>>
>
>The source of the problem is actually the DYN_OUT bit in REVCTL. All
>examples given in FX2 TRM tell us to set the bits in REVCTL(REVCTL=0x03).
>The DYN_out bit when set disables the auto-arming(TRM 15.5.9). But
>configuration of FIFO registers require DYN_OUT to be set. The
REVCTL=0x03
>is actually only required before we reset the FIFO buffers. Hence the
trick
>is to reset the REVCTL(REVCTL=0x00) after resetting the FIFO, and
>EPxFIFOCFG must be done after resetting REVCTL. Try this sequence and see
>if it works.
>1. IFCONFIG=??; //Your choice of configuration
>2. REVCTL=0x03;
> SYNCDELAY
>3. Configure endpoints
> EP2CFG=0xA2; //endpoint2 as outendpoint
> EP6CFG=0xE2; //endpoint6 an inendpoint
>4. Fifo reset
> FIFORESET=0x80;
> FIFORESET=0x02;
> FIFORESET=0x06;
> FIFORESET=0X00;
>5. Prime outendpoints
> OUTPKTEND=0x82;
> OUTPKTEND=0x82; //2 times for double buffer
> SYNCDELAY;
>6. Now that fifo has been reset we can revert the REVCTL bits for autoarm
> REVCTL=0x00;
> SYNCDELAY;
>7. Configure FIFO
> EP2FIFOCFG=bmAUTOOUT; //set the commit
> EP6FIFOCFG=bmAUTOIN; //you can also set WORDWIDE here
>8. Set autoinlen for inendpoints
> EP6AUTOINLENH=??;
> EP6AUTOINLENL=??;
> SYNCDELAY;
>We are done. The example given above use endpoint2 as out endpoint and
>endpoint6 as in endpoint. With 8 bit FIFO access.
>
>
>
>
>
>---------------------------------------
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>http://www.EmbeddedRelated.com
>

I've been looking for solution for the FIFO-reset problem, and found this
post via Google. I've tested the suggestions, and here go my conclusions:

Actually, You need to combine both suggestions given above. :)
So:
- SET IFCONFIG as required
- SET REVCTL=3
- configure endpoints (here: 2, 4 - OUT, 6, 8 - IN, all in bulk mode,
double buffered):
EP2CFG = 0xA2;
EP4CFG = 0xa0;
EP6CFG = 0xe2;
EP8CFG = 0xe0;
SYNCDELAY;

- zero EPxFIFOCFG:
EP2FIFOCFG=0;
SYNCDELAY;
EP4FIFOCFG=0;
SYNCDELAY;
EP6FIFOCFG=0;
SYNCDELAY;
EP8FIFOCFG=0;
SYNCDELAY;

- reset FIFO, YES, You can reset all fifos at once :)
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x8f;
SYNCDELAY;
/* FIFORESET = 0x84;
SYNCDELAY;
FIFORESET = 0x86;
SYNCDELAY;
FIFORESET = 0x88;
SYNCDELAY;
*/
FIFORESET = 0x00;
SYNCDELAY;

- deal with the end of out packets....REVCTL.0 MUST NOT be 0 here...
OUTPKTEND = 0x8f;
SYNCDELAY;
OUTPKTEND = 0x8f;
SYNCDELAY;
/* OUTPKTEND = 0x84;
SYNCDELAY;
OUTPKTEND = 0x84;
SYNCDELAY;
INPKTEND = 0x86;
SYNCDELAY;
INPKTEND = 0x86;
SYNCDELAY;
INPKTEND = 0x88;
SYNCDELAY;
INPKTEND = 0x88;
SYNCDELAY;
*/
- zero REVCTL
REVCTL=0;
SYNCDELAY;

- configure fifos as required...
EP2FIFOCFG = ...;
SYNCDELAY;
EP2FIFOPFH = ...;
SYNCDELAY;
EP2FIFOPFL = ...;
SYNCDELAY;

EP4FIFOCFG = ...;
SYNCDELAY;
EP4FIFOPFH = ...;
SYNCDELAY;
EP4FIFOPFL = ...;
SYNCDELAY;

EP6FIFOCFG = ...;
SYNCDELAY;
EP6FIFOPFH = ...;
SYNCDELAY;
EP6FIFOPFL = ...;
SYNCDELAY;

EP8FIFOCFG = ...;
SYNCDELAY;
EP8FIFOPFH = ...;
SYNCDELAY;
EP8FIFOPFL = ...;
SYNCDELAY;

EP6AUTOINLENH = ...;
SYNCDELAY;
EP6AUTOINLENL = ...;
SYNCDELAY;
EP8AUTOINLENH = ...;
SYNCDELAY;
EP8AUTOINLENL = ...;
SYNCDELAY;
- and ...

You're done :)

Regards.



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