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From: Justas P on 21 Nov 2009 17:06 Hi there, a newbie question, and I would be grateful for a response or at least hint where to look(read) for information. My problem is: I have two synchronisation domains. One device (A) is running at a 2.048 frequency. Then there is a STM32 microcontroller (B) that is using 8 MHz clock source. Dev A gives out NRZ data stream and accept NRZ data stream. I want to send and receive data eg: A <-> B. To do that I am planing to use CPLD to convert to/from parallel 8 bit data to serial NRZ stream. The question is how to organise data flow from CPLD to STM32. STM will be running at 72 MHz so I don't want to waist cycles. My idea is that once CPLD receives 8 bits of data from dev A, it copies data from shift register to a register and raises an interrupt to STM (or use internal counter), that data is ready (that would come at 2,048/8 = 256 KHz intervals, and that is perfect for me). But I can't figure out a way how to use same data lines for both writing/reading? Is there a better way than to mimic asynchronous memory interface with RDB/DSB and WRB/RWB? Please keep in mind that I only have 2 memory addresses - data to be transmitted and data to be read? Thanks in advance! Justin
From: linnix on 21 Nov 2009 18:39 On Nov 21, 2:06 pm, Justas P <justas.pode...(a)gmail.com> wrote: > Hi there, > > a newbie question, and I would be grateful for a response or at least > hint where to look(read) for information. > > My problem is: > I have two synchronisation domains. One device (A) is running at a > 2.048 frequency. Then there is a STM32 microcontroller (B) that is > using 8 MHz clock source. Dev A gives out NRZ data stream and accept > NRZ data stream. I want to send and receive data eg: A <-> B. To do > that I am planing to use CPLD to convert to/from parallel 8 bit data > to serial NRZ stream. > > The question is how to organise data flow from CPLD to STM32. STM will > be running at 72 MHz so I don't want to waist cycles. My idea is that > once CPLD receives 8 bits of data from dev A, it copies data from > shift register to a register and raises an interrupt to STM (or use > internal counter), that data is ready (that would come at 2,048/8 = > 256 KHz intervals, and that is perfect for me). But I can't figure out > a way how to use same data lines for both writing/reading? Is there a > better way than to mimic asynchronous memory interface with RDB/DSB > and WRB/RWB? Please keep in mind that I only have 2 memory addresses - > data to be transmitted and data to be read? > > Thanks in advance! > Justin You can do: device -> serial to parallel -> FIFO -> STM32 -> FIFO -> parallel to serial -> device. Two to four levels FIFO should be enough to minimize interrupts for the STM32. If your micro can't process and store data fast enough, you have bigger problems anyway.
From: Rob Gaddi on 23 Nov 2009 12:20 On Sat, 21 Nov 2009 14:06:51 -0800 (PST) Justas P <justas.poderys(a)gmail.com> wrote: > Hi there, > > a newbie question, and I would be grateful for a response or at least > hint where to look(read) for information. > > My problem is: > I have two synchronisation domains. One device (A) is running at a > 2.048 frequency. Then there is a STM32 microcontroller (B) that is > using 8 MHz clock source. Dev A gives out NRZ data stream and accept > NRZ data stream. I want to send and receive data eg: A <-> B. To do > that I am planing to use CPLD to convert to/from parallel 8 bit data > to serial NRZ stream. > > The question is how to organise data flow from CPLD to STM32. STM will > be running at 72 MHz so I don't want to waist cycles. My idea is that > once CPLD receives 8 bits of data from dev A, it copies data from > shift register to a register and raises an interrupt to STM (or use > internal counter), that data is ready (that would come at 2,048/8 = > 256 KHz intervals, and that is perfect for me). But I can't figure out > a way how to use same data lines for both writing/reading? Is there a > better way than to mimic asynchronous memory interface with RDB/DSB > and WRB/RWB? Please keep in mind that I only have 2 memory addresses - > data to be transmitted and data to be read? > > Thanks in advance! > Justin Use the CPLD as a UART, go into a dedicated UART peripheral on the STM? That gives you all your communications in two wires, one RX and one TX, and uses the state machine they've already built into the peripheral rather than your core clock cycles. -- Rob Gaddi, Highland Technology Email address is currently out of order
From: -jg on 23 Nov 2009 13:30 sOn Nov 22, 11:06 am, Justas P <justas.pode...(a)gmail.com> wrote: > Hi there, > > a newbie question, and I would be grateful for a response or at least > hint where to look(read) for information. > > My problem is: > I have two synchronisation domains. One device (A) is running at a > 2.048 frequency. Then there is a STM32 microcontroller (B) that is > using 8 MHz clock source. Dev A gives out NRZ data stream and accept > NRZ data stream. I want to send and receive data eg: A <-> B. To do > that I am planing to use CPLD to convert to/from parallel 8 bit data > to serial NRZ stream. > > The question is how to organise data flow from CPLD to STM32. STM will > be running at 72 MHz so I don't want to waist cycles. My idea is that > once CPLD receives 8 bits of data from dev A, it copies data from > shift register to a register and raises an interrupt to STM (or use > internal counter), that data is ready (that would come at 2,048/8 = > 256 KHz intervals, and that is perfect for me). But I can't figure out > a way how to use same data lines for both writing/reading? Is there a > better way than to mimic asynchronous memory interface with RDB/DSB > and WRB/RWB? Please keep in mind that I only have 2 memory addresses - > data to be transmitted and data to be read? > > Thanks in advance! > Justin This is hard to decipher ? You say NRZ, but then say the 2nd uC runs at 2.048MHz and can accept data at 2,048/8 byte rate - That's 1 bit every clock, and it is rare for controllers to accept ANY serial stream at the SYSCLK rate. UARTS are /8 or /16, and SPI can get to /2 on some for master, but slave is usually slower again. Then you say 8Mhz and 72Mhz, so it is not easy to see that speeds you really mean, where.... ? From a pure data flow angle, yes you can use a CPLD as a parallel to serial, and parallel-side you can use SRAM model (OE on read, is std SRAM direction control) You may want to include a flag pathway, typically these are TxReady, RxNew, and TxWait. (depends a little on who is considered the master) Or, if speed is vital, you can skip polling TxReady, and time-pace Sends, but here an 'Oops' sticky flag can be nice to add, to catch if this ever messes up. I'd also look at the SSC/SPI speeds of both sides, and see if existing peripherals can be used : ie is the CPLD _really_ needed ?
From: Justas P on 23 Nov 2009 16:37
> I'd also look at the SSC/SPI speeds of both sides, > and see if existing peripherals can be used : ie > is the CPLD _really_ needed ? I think, I might not have been really good at describing my problem. Yes, I would love to go with integrated uarts/SPIs in ARM uC, but a device that I want to connect to ARM outputs data like this: +-----+ | dev | -- Serial data out1 (NRZ) | | --- Serial data out1 clock | | --- Serial data in1 (NRZ) | | --- Serial data in1 clock | | -- Serial data out2 (NRZ) | | --- Serial data out2 clock | | --- Serial data in2 (NRZ) +-----+ --- Serial data in2 clock Clock is 2,048MHz and all 4 clocks are independent. My idea is to feed these 8 lines into CPLD, serialize/deserialize them and then have a 8bit wide bus to uC. Since I would do 1:8 deserializing, I would get interrupt from CPLD to take or put data at appx 4x256KHz. Maybe I am missing something, but I don't see a way how to multiplex SPI's since uC have only 2 and CPLD with serializer/deserializer seems like the only option. |