jfet as current source, temp dependence in-theory question
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From: Jon Kirwan on 11 Apr 2010 19:16 I've not used JFETs before and was thinking about them first as high impedance current sources to get started learning more about them. (I already gather that their potentially very high input impedance and low Ciss is a good thing and I'm broadly aware that FET and BJT input opamps divide their world into low bias current vs low offset voltage camps.) Looking over a datasheet on one, I see a chart picturing Id vs Vgs (for one specific Idss) and illustrating several curves for different temperatures. I note in this case that they all cross at Id=10mA (and on this part, that happens in the selected world of this datasheet at Vgs=-0.4V.) That suggests that setting things up for Id=10mA would seem to mitigate temperature variation in a simple current source based on this device. (Similar on the real part, but not necessarily exactly there, of course.) However, there is a complication. I'd like that current source to also be relatively _flat_ over the Vds compliance range as well as temperature. Looking over the Id vs Vds curves, it gets pretty nice and flat but close to the pinch-off Vgs(off) and not close to Id=10mA, where the d(Vds)/d(Id) slope is closer to about 3k ohms, compared to about 26k ohms at Id=1mA. So it seems to get the temperature stability tighter I have to loosen up on stability vs Vd, in this part. Is that generally the case for simple JFET current sources? Am I reading this wrong? (If right, are there JFETs that get both of these benefits relatively well optimized at close to the same point of operation?) Jon
From: Jim Thompson on 11 Apr 2010 20:20 On Sun, 11 Apr 2010 16:16:32 -0700, Jon Kirwan <jonk(a)infinitefactors.org> wrote: >I've not used JFETs before and was thinking about them first >as high impedance current sources to get started learning >more about them. > >(I already gather that their potentially very high input >impedance and low Ciss is a good thing and I'm broadly aware >that FET and BJT input opamps divide their world into low >bias current vs low offset voltage camps.) > >Looking over a datasheet on one, I see a chart picturing Id >vs Vgs (for one specific Idss) and illustrating several >curves for different temperatures. I note in this case that >they all cross at Id=10mA (and on this part, that happens in >the selected world of this datasheet at Vgs=-0.4V.) That >suggests that setting things up for Id=10mA would seem to >mitigate temperature variation in a simple current source >based on this device. (Similar on the real part, but not >necessarily exactly there, of course.) > >However, there is a complication. I'd like that current >source to also be relatively _flat_ over the Vds compliance >range as well as temperature. Looking over the Id vs Vds >curves, it gets pretty nice and flat but close to the >pinch-off Vgs(off) and not close to Id=10mA, where the >d(Vds)/d(Id) slope is closer to about 3k ohms, compared to >about 26k ohms at Id=1mA. So it seems to get the temperature >stability tighter I have to loosen up on stability vs Vd, in >this part. > >Is that generally the case for simple JFET current sources? >Am I reading this wrong? (If right, are there JFETs that get >both of these benefits relatively well optimized at close to >the same point of operation?) > >Jon Do you have any problem using an OpAmp to stabilize the whole thing? ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | The only thing bipartisan in this country is hypocrisy
From: Jon Kirwan on 12 Apr 2010 01:39 On Sun, 11 Apr 2010 17:20:54 -0700, Jim Thompson <To-Email-Use-The-Envelope-Icon(a)On-My-Web-Site.com> wrote: >On Sun, 11 Apr 2010 16:16:32 -0700, Jon Kirwan ><jonk(a)infinitefactors.org> wrote: > >>I've not used JFETs before and was thinking about them first >>as high impedance current sources to get started learning >>more about them. >> >>(I already gather that their potentially very high input >>impedance and low Ciss is a good thing and I'm broadly aware >>that FET and BJT input opamps divide their world into low >>bias current vs low offset voltage camps.) >> >>Looking over a datasheet on one, I see a chart picturing Id >>vs Vgs (for one specific Idss) and illustrating several >>curves for different temperatures. I note in this case that >>they all cross at Id=10mA (and on this part, that happens in >>the selected world of this datasheet at Vgs=-0.4V.) That >>suggests that setting things up for Id=10mA would seem to >>mitigate temperature variation in a simple current source >>based on this device. (Similar on the real part, but not >>necessarily exactly there, of course.) >> >>However, there is a complication. I'd like that current >>source to also be relatively _flat_ over the Vds compliance >>range as well as temperature. Looking over the Id vs Vds >>curves, it gets pretty nice and flat but close to the >>pinch-off Vgs(off) and not close to Id=10mA, where the >>d(Vds)/d(Id) slope is closer to about 3k ohms, compared to >>about 26k ohms at Id=1mA. So it seems to get the temperature >>stability tighter I have to loosen up on stability vs Vd, in >>this part. >> >>Is that generally the case for simple JFET current sources? >>Am I reading this wrong? (If right, are there JFETs that get >>both of these benefits relatively well optimized at close to >>the same point of operation?) >> >>Jon > >Do you have any problem using an OpAmp to stabilize the whole thing? At this stage, I'm just trying to make sure I can follow the datasheet, when thinking about one of the simplest JFET circuits to use. As I wrote, I've not used them before and I'm only now starting to look more closely at them. I'm just a hobbyist and try and take things one step at a time... explore the problems first and make sure I grasp enough of the basics. If the problem were a specific current source, a discrete JFET might not even be on the table, anyway. This is about understanding JFETs better, not building a real current sink. The current sink is a fencing foil for learning about how to read JFET datasheets and perhaps learn a little about the scattering of real JFETs that I might find, were I to look further than I have. Jon
From: Tim Williams on 12 Apr 2010 02:54 AFAIK, JFETs all behave pretty much the same way. There are only two fundamental parameters that vary with manufacture, Rds(on) and Vgs(off). Rds(on) is the resistance of the channel when it's not pinched off at all (and not enhanced by injected charge carriers!), and ranges from ~2.5k (2N4338) to single digit ohms (J107, etc.). (I don't think anyone makes monster JFETs competitive with fractional-Rds(on) MOSFETs, nor are there really any manufacturers making HV JFETs.) Pinchoff voltage varies from maybe -0.3V to -8V or lower. In particular, these spreads occur within the same part or family, so if you need a particular current or offset or something, you'll have to test and select parts to be sure, or make the circuit significantly adjustable. You can plug these numbers into the JFET equation (I don't have it handy, unfortunately; check Google) and basically know everything about it (except for temperature dependancy). The variation in Rds(on), Vgs(off) and Idss are shown in Figure 10: http://www.onsemi.com/pub_link/Collateral/MPF4392-D.PDF You can expect other JFETs to follow a similar pattern within their respective raneg. Temperature compensation seems to go in the same general direction (this is going to be governed by Rds(on) rising with temperature, and whatever happens to Vgs(off), which doesn't seem to be well specified?). Plots like Tim -- Deep Friar: a very philosophical monk. Website: http://webpages.charter.net/dawill/tmoranwms "Jon Kirwan" <jonk(a)infinitefactors.org> wrote in message news:7tb5s5hppprjcdacle9mticttlt7u1u9hn(a)4ax.com... > At this stage, I'm just trying to make sure I can follow the > datasheet, when thinking about one of the simplest JFET > circuits to use. As I wrote, I've not used them before and > I'm only now starting to look more closely at them. I'm just > a hobbyist and try and take things one step at a time... > explore the problems first and make sure I grasp enough of > the basics. > > If the problem were a specific current source, a discrete > JFET might not even be on the table, anyway. This is about > understanding JFETs better, not building a real current sink. > The current sink is a fencing foil for learning about how to > read JFET datasheets and perhaps learn a little about the > scattering of real JFETs that I might find, were I to look > further than I have. > > Jon
From: Tim Williams on 12 Apr 2010 03:03
Oops, > AFAIK, JFETs all behave pretty much the same way. There are only two > fundamental parameters that vary with manufacture, Rds(on) and Vgs(off). > > Rds(on) is the resistance of the channel when it's not pinched off at all > (and not enhanced by injected charge carriers!), and ranges from ~2.5k > (2N4338) to single digit ohms (J107, etc.). (I don't think anyone makes > monster JFETs competitive with fractional-Rds(on) MOSFETs, nor are there > really any manufacturers making HV JFETs.) > > Pinchoff voltage varies from maybe -0.3V to -8V or lower. In particular, > these spreads occur within the same part or family, so if you need a > particular current or offset or something, you'll have to test and select > parts to be sure, or make the circuit significantly adjustable. > > You can plug these numbers into the JFET equation (I don't have it handy, > unfortunately; check Google) and basically know everything about it > (except for temperature dependancy). The variation in Rds(on), Vgs(off) > and Idss are shown in Figure 10: > http://www.onsemi.com/pub_link/Collateral/MPF4392-D.PDF > You can expect other JFETs to follow a similar pattern within their > respective raneg. > > Temperature compensation seems to go in the same general direction (this > is going to be governed by Rds(on) rising with temperature, and whatever > happens to Vgs(off), which doesn't seem to be well specified?). Plots > like top row of page 3: http://www.fairchildsemi.com/ds/J1%2FJ113.pdf show points of current stability, but at nonzero Vgs, which is kind of sucky. If you have the voltage overhead, you could use a source resistor to self-bias it to this point. Curiously, the two plots show this crossing at approximately the same point (3-5mA) for all Vgs(off) values given. In the Vgs = 0 region, the tempco is negative, or.... I think they made a typo on the top-left plot: the Vgs(off) = -2V curves seem to be labeled in reverse order with respect to temperature! The other three series seem to be in the correct order at least... Anyway, negative tempco, and the percentagewise change should be fairly similar across transistors. Let's see... it's hard to tell here because the larger curves are cut off, you don't get to see the -55C intercept. It seems to have a lower tempco for lower Vgs(off)'s, though. That would make compensating a FET CCS + source follower (i.e., a zero-offset follower) somewhat inconvienient. Tim -- Deep Friar: a very philosophical monk. Website: http://webpages.charter.net/dawill/tmoranwms |