From: bouthouri on
I will use Intel StrataFlash Parallel NOR Flash PROM to store two . bit
files .

I have been able to generate the two files. prm &. mcs after having
1) prepare a PromFile.
2) Prom supporting multiple Design versions .
3) Adding the first and the second Bitsream bitsream


after that I want to configure the parallel Prom but I can not make it? is
what I have to configure the FPGA as or NO?? ...

Can someone help me??? thank you in advance ..





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From: Tim Wescott on
bouthouri wrote:
> I will use Intel StrataFlash Parallel NOR Flash PROM to store two . bit
> files .
>
> I have been able to generate the two files. prm &. mcs after having
> 1) prepare a PromFile.
> 2) Prom supporting multiple Design versions .
> 3) Adding the first and the second Bitsream bitsream
>
>
> after that I want to configure the parallel Prom but I can not make it? is
> what I have to configure the FPGA as or NO?? ...
>
> Can someone help me??? thank you in advance ..

Your question isn't clear, so I'll answer what I think you most likely
meant to ask:

So you want to have a flash chip that has not one, but two FPGA images,
and you want to somehow select which image gets loaded. This problem
would be trivial if you were loading the FPGA from a processor, so I
assume that you want to have the FPGA self-load (in which case I wonder
why you're not posting this to the FPGA group, or at least
cross-posting. Bad You if you're multiple posting).

If the interface between the FPGA and the flash is general purpose
enough, why not just load one image in the space addressed with the
highest-order address pin at 0, and the other image in the space
addressed with the highest-order address pin at 1? Then control that
pin separately from the FPGA to select the correct image to load.

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
From: bouthouri on
Thank you very much Mr. Tim Wescott

I work on Spartan-3E Starter Kit Board, of which there are startaflash
Numonyx (128 Mbit)
.. After my research I found that I have to use a module MBT (Multiboot
Trigger) ... onn STARTUP
I find difficulty in understanding the principle .. Because I prepared the
two files. Bit
but I do not know if I need to prepare a VHDL code that will handle the
selection of a design or two we just need to configure the FPGA to use
Startaflash...

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