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From: san_jack on 10 Jul 2010 01:37
We are designing a circuit in FPGA which has many modules and each
operating at different clock frequencies (but,each clock will be multiple
of other). each module will be connected to other module in sequential
fashion. Module A (20KHz) --> Module B (10KHz) --> Module C (2KHz) -->
Module D (10KHz) --> Module E (20KHz).

What are the things do i need to consider while designing such circuits?

I use xilinx ISE webpack 12.1 and ISE simulator. Do we have to purchase any
other tools for verification of such designs?
From: Vladimir Vassilevsky on 10 Jul 2010 09:49


san_jack wrote:
> We are designing a circuit in FPGA which has many modules and each
> operating at different clock frequencies (but,each clock will be multiple
> of other). each module will be connected to other module in sequential
> fashion. Module A (20KHz) --> Module B (10KHz) --> Module C (2KHz) -->
> Module D (10KHz) --> Module E (20KHz).
>
> What are the things do i need to consider while designing such circuits?

If you are running at kHz speed, consider MCU or DSP instead of FPGA.

Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com
From: Tim Wescott on 10 Jul 2010 22:17
On 07/10/2010 06:49 AM, Vladimir Vassilevsky wrote:
>
>
> san_jack wrote:
>> We are designing a circuit in FPGA which has many modules and each
>> operating at different clock frequencies (but,each clock will be multiple
>> of other). each module will be connected to other module in sequential
>> fashion. Module A (20KHz) --> Module B (10KHz) --> Module C (2KHz) -->
>> Module D (10KHz) --> Module E (20KHz).
>>
>> What are the things do i need to consider while designing such circuits?
>
> If you are running at kHz speed, consider MCU or DSP instead of FPGA.

No kidding!

If there's some reason you can't use a processor, at least consider
aggressively trading off space for speed (a processor's a good way to do
that if the algorithm is big enough). Or just clock the whole thing at
20kHz, and put registers on the output such that module B only changes
every 2nd clock, module C every 10th, etc.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html
From: san_jack on 12 Jul 2010 01:21
I Hope, it should be "Or just clock the whole thing at 2kHz, and put
registers on the output such that module B only changes every 5th clock,
module A every 10th, etc.". Is my understanding correct?


>On 07/10/2010 06:49 AM, Vladimir Vassilevsky wrote:
>>
>>
>> san_jack wrote:
>>> We are designing a circuit in FPGA which has many modules and each
>>> operating at different clock frequencies (but,each clock will be
multiple
>>> of other). each module will be connected to other module in sequential
>>> fashion. Module A (20KHz) --> Module B (10KHz) --> Module C (2KHz) -->
>>> Module D (10KHz) --> Module E (20KHz).
>>>
>>> What are the things do i need to consider while designing such
circuits?
>>
>> If you are running at kHz speed, consider MCU or DSP instead of FPGA.
>
>No kidding!
>
>If there's some reason you can't use a processor, at least consider
>aggressively trading off space for speed (a processor's a good way to do
>that if the algorithm is big enough). Or just clock the whole thing at
>20kHz, and put registers on the output such that module B only changes
>every 2nd clock, module C every 10th, etc.
>
>--
>
>Tim Wescott
>Wescott Design Services
>http://www.wescottdesign.com
>
>Do you need to implement control loops in software?
>"Applied Control Theory for Embedded Systems" was written for you.
>See details at http://www.wescottdesign.com/actfes/actfes.html
>
From: rickman on 12 Jul 2010 01:36
No, you have missed the idea. If the entire circuit is clocked at 20
kHz, you can generate a signal that is asserted just once in every
other clock cycle which will enable the registers in the 10 kHz logic,
every other enable generates another enable (once in four clock
cycles) for the 5 kHz logic) and another enable asserted once in 10
clocks for the 2 kHz logic.

When you use enables on the registers the logic runs as a slower rate,
not a faster rate.

I don't mean to be pessimistic, but if you don't understand enabled
registers, you aren't likely to end up with a working design. Is this
a real project or a student exercise?

Rick


On Jul 12, 1:21 am, "san_jack" <sridar(a)n_o_s_p_a_m.kphsonline.com>
wrote:
> I Hope, it should be "Or just clock the whole thing at 2kHz, and put
> registers on the output such that module B only changes every 5th clock,
> module A every 10th, etc.". Is my understanding correct?
>
>
>
> >On 07/10/2010 06:49 AM, Vladimir Vassilevsky wrote:
>
> >> san_jack wrote:
> >>> We are designing a circuit in FPGA which has many modules and each
> >>> operating at different clock frequencies (but,each clock will be
> multiple
> >>> of other). each module will be connected to other module in sequential
> >>> fashion. Module A (20KHz) --> Module B (10KHz) --> Module C (2KHz) -->
> >>> Module D (10KHz) --> Module E (20KHz).
>
> >>> What are the things do i need to consider while designing such
> circuits?
>
> >> If you are running at kHz speed, consider MCU or DSP instead of FPGA.
>
> >No kidding!
>
> >If there's some reason you can't use a processor, at least consider
> >aggressively trading off space for speed (a processor's a good way to do
> >that if the algorithm is big enough).  Or just clock the whole thing at
> >20kHz, and put registers on the output such that module B only changes
> >every 2nd clock, module C every 10th, etc.
>
> >--
>
> >Tim Wescott
> >Wescott Design Services
> >http://www.wescottdesign.com
>
> >Do you need to implement control loops in software?
> >"Applied Control Theory for Embedded Systems" was written for you.
> >See details athttp://www.wescottdesign.com/actfes/actfes.html
>
>

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