mxc: Add board support for the i.MX51 babbage board
in [Kernel]
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From: Sascha Hauer on 4 Dec 2009 05:30 On Fri, Dec 04, 2009 at 04:47:05AM +0200, Amit Kucheria wrote: > Add basic clock support, cpu identification, I/O mapping and serial port. Boot > tested on Freescale Babbage 2.5 board. > > Support for FEC ethernet device is also added to allow NFS-root but needs the > fixes from the following patches to get onboard-ethernet working > > Signed-off-by: Amit Kucheria <amit.kucheria(a)canonical.com> > --- > arch/arm/mach-mx5/board-mx51_babbage.c | 141 +++++ > arch/arm/mach-mx5/clock.c | 817 +++++++++++++++++++++++++++ > arch/arm/mach-mx5/cpu.c | 46 ++ > arch/arm/mach-mx5/crm_regs.h | 685 ++++++++++++++++++++++ > arch/arm/mach-mx5/devices.c | 90 +++ > arch/arm/mach-mx5/devices.h | 4 + > arch/arm/mach-mx5/mm.c | 86 +++ > arch/arm/plat-mxc/include/mach/iomux-mx51.h | 309 ++++++++++ > arch/arm/plat-mxc/include/mach/mx51.h | 481 ++++++++++++++++ > 9 files changed, 2659 insertions(+), 0 deletions(-) > create mode 100644 arch/arm/mach-mx5/board-mx51_babbage.c > create mode 100644 arch/arm/mach-mx5/clock.c > create mode 100644 arch/arm/mach-mx5/cpu.c > create mode 100644 arch/arm/mach-mx5/crm_regs.h > create mode 100644 arch/arm/mach-mx5/devices.c > create mode 100644 arch/arm/mach-mx5/devices.h > create mode 100644 arch/arm/mach-mx5/mm.c > create mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx51.h > create mode 100644 arch/arm/plat-mxc/include/mach/mx51.h > > diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c > new file mode 100644 > index 0000000..a1bc9c4 > --- /dev/null > +++ b/arch/arm/mach-mx5/board-mx51_babbage.c > @@ -0,0 +1,141 @@ > +/* > + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. > + * Copyright 2009 Amit Kucheria <amit.kucheria(a)canonical.com> All Rights Reserved. > + * > + * The code contained herein is licensed under the GNU General Public > + * License. You may obtain a copy of the GNU General Public License > + * Version 2 or later at the following locations: > + * > + * http://www.opensource.org/licenses/gpl-license.html > + * http://www.gnu.org/copyleft/gpl.html > + */ > + > +#include <linux/init.h> > +#include <linux/platform_device.h> > +#include <mach/common.h> > +#include <mach/hardware.h> > +#include <asm/irq.h> > +#include <asm/setup.h> > +#include <asm/mach-types.h> > +#include <asm/mach/arch.h> > +#include <asm/mach/time.h> > +#include <mach/memory.h> > +#include <mach/imx-uart.h> > +#include <mach/iomux-mx51.h> > + > +#include "crm_regs.h" > +#include "devices.h" > + > +extern void __init mx51_babbage_io_init(void); > + > +/* Pad control groupings */ > +#define MX51_UART1_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH) > +#define MX51_UART2_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) > +#define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) > + > +/* UART1 */ > +#define MX51_BABBAGE_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) > +#define MX51_BABBAGE_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) > +#define MX51_BABBAGE_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL) > +#define MX51_BABBAGE_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL) > + > +/* UART2 */ > +#define MX51_BABBAGE_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL) > +#define MX51_BABBAGE_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL) > + > +/* UART3 */ > +#define MX51_BABBAGE_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL) > +#define MX51_BABBAGE_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL) > +#define MX51_BABBAGE_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL) > +#define MX51_BABBAGE_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL) > + These should go as generic versions to arch/arm/plat-mxc/include/mach/iomux-mx51.h. > + > +#define MX51_BABBAGE_PAD_GPIO_1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)) > + > +static struct platform_device *devices[] __initdata = { > + &mxc_fec_device, > +}; > + > +static struct pad_desc mx51babbage_pads[] = { > + /* UART1 */ > + MX51_BABBAGE_PAD_UART1_RXD__UART1_RXD, > + MX51_BABBAGE_PAD_UART1_TXD__UART1_TXD, > + MX51_BABBAGE_PAD_UART1_RTS__UART1_RTS, > + MX51_BABBAGE_PAD_UART1_CTS__UART1_CTS, > + > + /* UART2 */ > + MX51_BABBAGE_PAD_UART2_RXD__UART2_RXD, > + MX51_BABBAGE_PAD_UART2_TXD__UART2_TXD, > + > + /* UART3 */ > + MX51_BABBAGE_PAD_EIM_D25__UART3_RXD, > + MX51_BABBAGE_PAD_EIM_D26__UART3_TXD, > + MX51_BABBAGE_PAD_EIM_D27__UART3_RTS, > + MX51_BABBAGE_PAD_EIM_D24__UART3_CTS, > +}; > + > +/* Serial ports */ > +#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) > +static struct imxuart_platform_data uart_pdata = { > + .flags = IMXUART_HAVE_RTSCTS, > +}; > + > +static inline void mxc_init_imx_uart(void) > +{ > + mxc_register_device(&mxc_uart_device0, &uart_pdata); > + mxc_register_device(&mxc_uart_device1, &uart_pdata); > + mxc_register_device(&mxc_uart_device2, &uart_pdata); > +} > +#else /* !SERIAL_IMX */ > +static inline void mxc_init_imx_uart(void) > +{ > +} > +#endif /* SERIAL_IMX */ > + > +/* > + * Board specific fixup function. It is called by \b setup_arch() in > + * setup.c file very early on during kernel starts. It allows the user to > + * statically fill in the proper values for the passed-in parameters. None of > + * the parameters is used currently. > + * > + * @param desc pointer to \b struct \b machine_desc > + * @param tags pointer to \b struct \b tag > + * @param cmdline pointer to the command line > + * @param mi pointer to \b struct \b meminfo > + */ > +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, > + char **cmdline, struct meminfo *mi) > +{ > + /* Nothing! */ > +} Please remove this function > + > +/* > + * Board specific initialization. > + */ > +static void __init mxc_board_init(void) > +{ > + mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, ARRAY_SIZE(mx51babbage_pads)); > + mxc_init_imx_uart(); > + platform_add_devices(devices, ARRAY_SIZE(devices)); > +} > + > +static void __init mx51_babbage_timer_init(void) > +{ > + mx51_clocks_init(32768, 24000000, 22579200, 24576000); > +} > + > +static struct sys_timer mxc_timer = { > + .init = mx51_babbage_timer_init, > +}; > + > +MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") > + /* Maintainer: Amit Kucheria <amit.kucheria(a)canonical.com> */ > + .phys_io = AIPS1_BASE_ADDR, > + .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, > + .boot_params = PHYS_OFFSET + 0x100, > + .fixup = fixup_mxc_board, > + .map_io = mx51_map_io, > + .init_irq = mx51_init_irq, > + .init_machine = mxc_board_init, > + .timer = &mxc_timer, > +MACHINE_END > diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c > new file mode 100644 > index 0000000..7fdfcbc > --- /dev/null > +++ b/arch/arm/mach-mx5/clock.c > @@ -0,0 +1,817 @@ > +/* > + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. > + * Copyright 2009 Amit Kucheria <amit.kucheria(a)canonical.com>. All Rights Reserved. > + * > + * The code contained herein is licensed under the GNU General Public > + * License. You may obtain a copy of the GNU General Public License > + * Version 2 or later at the following locations: > + * > + * http://www.opensource.org/licenses/gpl-license.html > + * http://www.gnu.org/copyleft/gpl.html > + */ > + > +#include <linux/mm.h> > +#include <linux/delay.h> > +#include <linux/clk.h> > +#include <linux/io.h> > + > +#include <asm/clkdev.h> > + > +#include <mach/hardware.h> > +#include <mach/common.h> > +#include <mach/clock.h> > + > +#include "crm_regs.h" > + > +static unsigned long pll_base[] = { > + (unsigned long)MXC_DPLL1_BASE, > + (unsigned long)MXC_DPLL2_BASE, > + (unsigned long)MXC_DPLL3_BASE, These casts show that this array should be of type void __iomem *. > +}; > + > +/* External clock values passed-in by the board code */ > +static unsigned long external_high_reference, external_low_reference; > +static unsigned long oscillator_reference, ckih2_reference; > + > +static struct clk osc_clk; > +static struct clk pll1_main_clk; > +static struct clk pll1_sw_clk; > +static struct clk pll2_sw_clk; > +static struct clk pll3_sw_clk; > +static struct clk lp_apm_clk; > +static struct clk periph_apm_clk; > +static struct clk ahb_clk; > +static struct clk ipg_clk; > + > +#define SPIN_DELAY 1000000 /* in nanoseconds */ > + > +extern void propagate_rate(struct clk *clk); This is not used. > + > +static int _clk_ccgr_enable(struct clk *clk) > +{ > + u32 reg; > + > + reg = __raw_readl(clk->enable_reg); > + reg |= MXC_CCM_CCGR_MOD_ON << clk->enable_shift; > + __raw_writel(reg, clk->enable_reg); > + > + return 0; > +} > + > +static void _clk_ccgr_disable(struct clk *clk) > +{ > + u32 reg; > + reg = __raw_readl(clk->enable_reg); > + reg &= ~(MXC_CCM_CCGR_MOD_OFF << clk->enable_shift); > + __raw_writel(reg, clk->enable_reg); > + > +} > + > +static void _clk_ccgr_disable_inwait(struct clk *clk) > +{ > + u32 reg; > + > + reg = __raw_readl(clk->enable_reg); > + reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift); > + reg |= MXC_CCM_CCGR_MOD_IDLE << clk->enable_shift; > + __raw_writel(reg, clk->enable_reg); > +} > + > +/* > + * For the 4-to-1 muxed input clock > + */ > +static inline u32 _get_mux(struct clk *parent, struct clk *m0, > + struct clk *m1, struct clk *m2, struct clk *m3) > +{ > + if (parent == m0) > + return 0; > + else if (parent == m1) > + return 1; > + else if (parent == m2) > + return 2; > + else if (parent == m3) > + return 3; > + else > + BUG(); > + > + return 0; > +} > + > +static inline unsigned long _get_pll_base(struct clk *pll) > +{ > + if (pll == &pll1_main_clk) > + return pll_base[0]; > + else if (pll == &pll2_sw_clk) > + return pll_base[1]; > + else if (pll == &pll3_sw_clk) > + return pll_base[2]; > + else > + BUG(); > + > + return 0; > +} > + > +static unsigned long _clk_pll_recalc(struct clk *clk) > +{ The original Freescale code stored the rate in clk->rate without returning the rate. As this is not true here, can we rename these functions to x_get_rate? Also, these leading underscores in the function names look like we have something to hide. We don't, right? > + long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; > + unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; > + unsigned long pllbase; > + s64 temp; > + unsigned long parent_rate; > + > + parent_rate = clk_get_rate(clk->parent); > + > + pllbase = _get_pll_base(clk); pllbase should be a void __iomem *. > + > + dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); > + pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; > + dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; > + > + if (pll_hfsm == 0) { > + dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); > + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); > + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); > + } else { > + dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP); > + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD); > + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN); > + } > + pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; > + mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; > + mfi = (mfi <= 5) ? 5 : mfi; > + mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; > + mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK; > + /* Sign extend to 32-bits */ > + if (mfn >= 0x04000000) { > + mfn |= 0xFC000000; > + mfn_abs = -mfn; > + } > + > + ref_clk = 2 * parent_rate; > + if (dbl != 0) > + ref_clk *= 2; > + > + ref_clk /= (pdf + 1); > + temp = (u64) ref_clk * mfn_abs; > + do_div(temp, mfd + 1); > + if (mfn < 0) > + temp = -temp; > + temp = (ref_clk * mfi) + temp; > + > + return temp; > +} > + > +static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) > +{ > + u32 reg; > + u32 pllbase; > + > + long mfi, pdf, mfn, mfd = 999999; > + s64 temp64; > + unsigned long quad_parent_rate; > + unsigned long pll_hfsm, dp_ctl; > + unsigned long parent_rate; > + > + parent_rate = clk_get_rate(clk->parent); > + > + pllbase = _get_pll_base(clk); > + > + quad_parent_rate = 4 * parent_rate; > + pdf = mfi = -1; > + while (++pdf < 16 && mfi < 5) > + mfi = rate * (pdf+1) / quad_parent_rate; > + if (mfi > 15) > + return -1; > + pdf--; > + > + temp64 = rate*(pdf+1) - quad_parent_rate*mfi; > + do_div(temp64, quad_parent_rate/1000000); > + mfn = (long)temp64; > + > + dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); > + /* use dpdck0_2 */ > + __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); > + pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; > + if (pll_hfsm == 0) { > + reg = mfi<<4 | pdf; > + __raw_writel(reg, pllbase + MXC_PLL_DP_OP); > + __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD); > + __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN); > + } else { > + reg = mfi<<4 | pdf; > + __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP); > + __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD); > + __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN); > + } Nitpick: Please add spaces on both sides of operators like << >> and * > + > + return 0; > +} > + > +static int _clk_pll_enable(struct clk *clk) > +{ > + u32 reg; > + u32 pllbase; > + struct timespec nstimeofday; > + struct timespec curtime; > + > + pllbase = _get_pll_base(clk); > + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; > + __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); > + > + /* Wait for lock */ > + getnstimeofday(&nstimeofday); > + while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF)) { > + getnstimeofday(&curtime); > + if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY) > + panic("pll relock failed\n"); > + } > + return 0; > +} > + > +static void _clk_pll_disable(struct clk *clk) > +{ > + u32 reg; > + u32 pllbase; > + > + pllbase = _get_pll_base(clk); > + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; > + __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); > +} > + > +static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent) > +{ > + u32 reg, mux; > + > + reg = __raw_readl(MXC_CCM_CCSR); > + > + if (parent == &pll1_main_clk) { > + reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL; > + __raw_writel(reg, MXC_CCM_CCSR); > + /* Set the step_clk parent to be lp_apm, to save power. */ > + mux = _get_mux(&lp_apm_clk, &lp_apm_clk, NULL, &pll2_sw_clk, > + &pll3_sw_clk); This looks wrong or at least unnecessary. _get_mux will always return 0 if called like this. > + reg = __raw_readl(MXC_CCM_CCSR); > + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | > + (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET); > + } else { > + if (parent == &lp_apm_clk) { > + reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; > + reg = __raw_readl(MXC_CCM_CCSR); > + mux = _get_mux(parent, &lp_apm_clk, NULL, &pll2_sw_clk, > + &pll3_sw_clk); We are inside if (parent == &lp_apm_clk), so _get_mux will always return 0 here aswell. > + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | > + (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET); > + } else { > + mux = _get_mux(parent, &lp_apm_clk, NULL, &pll2_sw_clk, > + &pll3_sw_clk); > + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | > + (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET); > + __raw_writel(reg, MXC_CCM_CCSR); > + reg = __raw_readl(MXC_CCM_CCSR); > + reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; > + > + } > + } > + __raw_writel(reg, MXC_CCM_CCSR); > + return 0; > +} > + > +static unsigned long _clk_pll1_sw_recalc(struct clk *clk) > +{ > + u32 reg, div; > + unsigned long parent_rate; > + > + parent_rate = clk_get_rate(clk->parent); > + > + div = 1; > + reg = __raw_readl(MXC_CCM_CCSR); > + > + if (clk->parent == &pll2_sw_clk) { > + div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >> > + MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1; > + } else if (clk->parent == &pll3_sw_clk) { > + div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >> > + MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1; > + } > + return parent_rate / div; > +} > + > +static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent) > +{ > + u32 reg; > + > + reg = __raw_readl(MXC_CCM_CCSR); > + > + if (parent == &pll2_sw_clk) { > + reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL; > + } else { > + reg = (reg & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL); > + reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL; You first clear the bit and then set the very same bit again. Looks like the first line is wrong. > + } > + __raw_writel(reg, MXC_CCM_CCSR); > + return 0; > +} > + > +static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent) > +{ > + u32 reg; > + > + if (parent == &osc_clk) > + reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL; > + else > + return -EINVAL; > + > + __raw_writel(reg, MXC_CCM_CCSR); > + > + return 0; > +} > + > +static unsigned long _clk_arm_recalc(struct clk *clk) > +{ > + u32 cacrr, div; > + unsigned long parent_rate; > + > + parent_rate = clk_get_rate(clk->parent); > + cacrr = __raw_readl(MXC_CCM_CACRR); > + div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1; > + > + return parent_rate / div; > +} > + > +static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent) > +{ > + u32 reg, mux; > + struct timespec nstimeofday; > + struct timespec curtime; > + > + mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL); > + > + reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK; > + reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET; > + __raw_writel(reg, MXC_CCM_CBCMR); > + > + getnstimeofday(&nstimeofday); > + while (__raw_readl(MXC_CCM_CDHIPR) & > + MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) { > + getnstimeofday(&curtime); > + if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY) > + panic("pll _clk_periph_apm_set_parent failed\n"); > + } > + return 0; > +} > + > +static unsigned long _clk_main_bus_recalc(struct clk *clk) > +{ > + return clk_get_rate(clk->parent); > +} > + > +static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent) > +{ > + u32 reg; > + > + if (parent == &pll2_sw_clk) { > + reg = __raw_readl(MXC_CCM_CBCDR) & > + ~MXC_CCM_CBCDR_PERIPH_CLK_SEL; > + } else if (parent == &periph_apm_clk) { > + reg = __raw_readl(MXC_CCM_CBCDR) | MXC_CCM_CBCDR_PERIPH_CLK_SEL; > + } else { > + return -EINVAL; > + } This reads better as reg = __raw_readl(MXC_CCM_CBCDR); if (parent == &pll2_sw_clk) reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL; else if (parent == &periph_apm_clk) reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL; else return -EINVAL; > + __raw_writel(reg, MXC_CCM_CBCDR); > + > + return 0; > +} > + > +static struct clk main_bus_clk = { > + .parent = &pll2_sw_clk, > + .set_parent = _clk_main_bus_set_parent, > + .get_rate = _clk_main_bus_recalc, > +}; > + > +static unsigned long _clk_ahb_recalc(struct clk *clk) > +{ > + u32 reg, div; > + unsigned long parent_rate; > + > + parent_rate = clk_get_rate(clk->parent); > + > + reg = __raw_readl(MXC_CCM_CBCDR); > + div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >> > + MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1; > + return parent_rate / div; > +} > + > + > +static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate) > +{ > + u32 reg, div; > + struct timespec nstimeofday; > + struct timespec curtime; > + unsigned long parent_rate; > + > + parent_rate = clk_get_rate(clk->parent); > + > + div = parent_rate / rate; > + if (div > 8 || div < 1 || ((parent_rate / div) != rate)) > + return -EINVAL; > + > + reg = __raw_readl(MXC_CCM_CBCDR); > + reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK; > + reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET; > + __raw_writel(reg, MXC_CCM_CBCDR); > + > + getnstimeofday(&nstimeofday); > + while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY) { > + getnstimeofday(&curtime); > + if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY) > + panic("_clk_ahb_set_rate failed\n"); > + } > + > + return 0; > +} > + > +static unsigned long _clk_ahb_round_rate(struct clk *clk, > + unsigned long rate) > +{ > + u32 div; > + unsigned long parent_rate; > + > + parent_rate = clk_get_rate(clk->parent); > + > + div = parent_rate / rate; > + if (div > 8) > + div = 8; > + else if (div == 0) > + div++; > + return parent_rate / div; > +} > + > + > +static int _clk_max_enable(struct clk *clk) > +{ > + u32 reg; > + > + _clk_ccgr_enable(clk); > + > + /* Handshake with MAX when LPM is entered. */ > + reg = __raw_readl(MXC_CCM_CLPCR); > + reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; > + __raw_writel(reg, MXC_CCM_CLPCR); > + > + return 0; > +} > + > +static void _clk_max_disable(struct clk *clk) > +{ > + u32 reg; > + > + _clk_ccgr_disable_inwait(clk); > + > + /* No Handshake with MAX when LPM is entered as its disabled. */ > + reg = __raw_readl(MXC_CCM_CLPCR); > + reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; > + __raw_writel(reg, MXC_CCM_CLPCR); > +} > + > +static unsigned long _clk_ipg_recalc(struct clk *clk) > +{ > + u32 reg, div; > + unsigned long parent_rate; > + > + parent_rate = clk_get_rate(clk->parent); > + > + reg = __raw_readl(MXC_CCM_CBCDR); > + div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >> > + MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1; > + > + return parent_rate / div; > +} > + > +static unsigned long _clk_ipg_per_recalc(struct clk *clk) > +{ > + u32 reg, prediv1, prediv2, podf; > + unsigned long parent_rate; > + > + parent_rate = clk_get_rate(clk->parent); > + > + if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) { > + /* the main_bus_clk is the one before the DVFS engine */ > + reg = __raw_readl(MXC_CCM_CBCDR); > + prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >> > + MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1; > + prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >> > + MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1; > + podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >> > + MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1; > + return parent_rate / (prediv1 * prediv2 * podf); > + } else if (clk->parent == &ipg_clk) { > + return clk_get_rate(&ipg_clk); return parent_rate? > + } else { > + BUG(); > + } > +} > + > +static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent) > +{ > + u32 reg, mux; > + > + reg = __raw_readl(MXC_CCM_CBCMR); > + mux = _get_mux(parent, &main_bus_clk, &lp_apm_clk, &ipg_clk, NULL); > + if (mux == 2) { > + reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; > + } else { > + reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; > + if (mux == 0) > + reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; > + else > + reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; > + } _get_mux does not seem to make sense in this context. How about: reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; if (parent == &ipg_clk) reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; else if (parent == &lp_apm_clk) reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; else if (parent != &main_bus_clk) return -EINVAL; > + __raw_writel(reg, MXC_CCM_CBCMR); > + > + return 0; > +} > + > +static unsigned long _clk_uart_recalc(struct clk *clk) > +{ > + u32 reg, prediv, podf; > + unsigned long parent_rate; > + > + parent_rate = clk_get_rate(clk->parent); > + > + reg = __raw_readl(MXC_CCM_CSCDR1); > + prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> > + MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1; > + podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> > + MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1; > + > + return parent_rate / (prediv * podf); > +} > + > +static int _clk_uart_set_parent(struct clk *clk, struct clk *parent) > +{ > + u32 reg, mux; > + > + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, > + &lp_apm_clk); > + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK; > + reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET; > + __raw_writel(reg, MXC_CCM_CSCMR1); > + > + return 0; > +} > + > +static unsigned long get_high_reference_clock_rate(struct clk *clk) > +{ > + return external_high_reference; > +} > + > +static unsigned long get_low_reference_clock_rate(struct clk *clk) > +{ > + return external_low_reference; > +} > + > +static unsigned long get_oscillator_reference_clock_rate(struct clk *clk) > +{ > + return oscillator_reference; > +} > + > +static unsigned long get_ckih2_reference_clock_rate(struct clk *clk) > +{ > + return ckih2_reference; > +} > + > +/* External high frequency clock */ > +static struct clk ckih_clk = { > + .get_rate = get_high_reference_clock_rate, > +}; > + > +static struct clk ckih2_clk = { > + .get_rate = get_ckih2_reference_clock_rate, > +}; > + > +static struct clk osc_clk = { > + .get_rate = get_oscillator_reference_clock_rate, > +}; > + > +/* External low frequency (32kHz) clock */ > +static struct clk ckil_clk = { > + .get_rate = get_low_reference_clock_rate, > +}; > + > +static struct clk pll1_main_clk = { > + .parent = &osc_clk, > + .get_rate = _clk_pll_recalc, > + .enable = _clk_pll_enable, > + .disable = _clk_pll_disable, > +}; > + > +/* Clock tree block diagram (WIP): > + * > + * PLL output -> | > + * | CCM Switcher -> CCM_CLK_ROOT_GEN -> > + * PLL bypass -> | > + * > + */ > + > +/* PLL1 SW supplies to ARM core */ > +static struct clk pll1_sw_clk = { > + .parent = &pll1_main_clk, > + .set_parent = _clk_pll1_sw_set_parent, > + .get_rate = _clk_pll1_sw_recalc, > +}; > + > +/* PLL2 SW supplies to AXI/AHB/IP buses */ > +static struct clk pll2_sw_clk = { > + .parent = &osc_clk, > + .get_rate = _clk_pll_recalc, > + .set_rate = _clk_pll_set_rate, > + .set_parent = _clk_pll2_sw_set_parent, > + .enable = _clk_pll_enable, > + .disable = _clk_pll_disable, > +}; > + > +/* PLL3 SW supplies to serial clocks like USB, SSI, etc. */ > +static struct clk pll3_sw_clk = { > + .parent = &osc_clk, > + .set_rate = _clk_pll_set_rate, > + .get_rate = _clk_pll_recalc, > + .enable = _clk_pll_enable, > + .disable = _clk_pll_disable, > +}; > + > +/* Low-power Audio Playback Mode clock */ > +static struct clk lp_apm_clk = { > + .parent = &osc_clk, > + .set_parent = _clk_lp_apm_set_parent, > +}; > + > +static struct clk periph_apm_clk = { > + .parent = &pll1_sw_clk, > + .set_parent = _clk_periph_apm_set_parent, > +}; > + > +static struct clk cpu_clk = { > + .parent = &pll1_sw_clk, > + .get_rate = _clk_arm_recalc, > +}; > + > +static struct clk ahb_clk = { > + .parent = &main_bus_clk, > + .get_rate = _clk_ahb_recalc, > + .set_rate = _clk_ahb_set_rate, > + .round_rate = _clk_ahb_round_rate, > +}; > + > +/* Main IP interface clock for access to registers */ > +static struct clk ipg_clk = { > + .parent = &ahb_clk, > + .get_rate = _clk_ipg_recalc, > +}; > + > +static struct clk ipg_perclk = { > + .parent = &lp_apm_clk, > + .get_rate = _clk_ipg_per_recalc, > + .set_parent = _clk_ipg_per_set_parent, > +}; > + > +static struct clk uart_root_clk = { > + .parent = &pll2_sw_clk, > + .get_rate = _clk_uart_recalc, > + .set_parent = _clk_uart_set_parent, > +}; > + > +static struct clk ahb_max_clk = { > + .parent = &ahb_clk, > + .enable_reg = MXC_CCM_CCGR0, > + .enable_shift = MXC_CCM_CCGR0_CG14_OFFSET, > + .enable = _clk_max_enable, > + .disable = _clk_max_disable, > +}; > + > +static struct clk aips_tz1_clk = { > + .parent = &ahb_clk, > + .secondary = &ahb_max_clk, > + .enable_reg = MXC_CCM_CCGR0, > + .enable_shift = MXC_CCM_CCGR0_CG12_OFFSET, > + .enable = _clk_ccgr_enable, > + .disable = _clk_ccgr_disable_inwait, > +}; > + > +static struct clk aips_tz2_clk = { > + .parent = &ahb_clk, > + .secondary = &ahb_max_clk, > + .enable_reg = MXC_CCM_CCGR0, > + .enable_shift = MXC_CCM_CCGR0_CG13_OFFSET, > + .enable = _clk_ccgr_enable, > + .disable = _clk_ccgr_disable_inwait, > +}; > + > +static struct clk gpt_32k_clk = { > + .id = 0, > + .parent = &ckil_clk, > +}; > + > +#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \ > + static struct clk name = { \ > + .id = i, \ > + .enable_reg = er, \ > + .enable_shift = es, \ > + .get_rate = gr, \ > + .set_rate = sr, \ > + .enable = _clk_ccgr_enable, \ > + .disable = _clk_ccgr_disable, \ > + .parent = p, \ > + .secondary = s, \ > + } > + > +/* DEFINE_CLOCK(name, id, enable_reg, enable_shift, get_rate, set_rate, parent, secondary); */ > + > +/* Shared peripheral bus arbiter */ > +DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGR0_CG0_OFFSET, NULL, NULL, &ipg_clk, NULL); > + > +/* UART */ > +DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGR1_CG4_OFFSET, NULL, NULL, &uart_root_clk, NULL); > +DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGR1_CG6_OFFSET, NULL, NULL, &uart_root_clk, NULL); > +DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGR1_CG8_OFFSET, NULL, NULL, &uart_root_clk, NULL); > +DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGR1_CG3_OFFSET, NULL, NULL, &ipg_clk, &aips_tz1_clk); > +DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGR1_CG5_OFFSET, NULL, NULL, &ipg_clk, &aips_tz1_clk); > +DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGR1_CG7_OFFSET, NULL, NULL, &ipg_clk, &spba_clk); > + > +/* GPT */ > +DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGR2_CG9_OFFSET, NULL, NULL, &ipg_perclk, NULL); > +DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGR2_CG10_OFFSET, NULL, NULL, &ipg_clk, NULL); > + > +/* FEC */ > +DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGR2_CG12_OFFSET, NULL, NULL, &ipg_clk, NULL); > + > +#define _REGISTER_CLOCK(d, n, c) \ > + { \ > + .dev_id = d, \ > + .con_id = n, \ > + .clk = &c, \ > + }, > + > +static struct clk_lookup lookups[] __initdata = { > + _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) > + _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) > + _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) > + _REGISTER_CLOCK(NULL, "gpt", gpt_clk) > + _REGISTER_CLOCK("fec.0", NULL, fec_clk) > +}; > + > +static void clk_tree_init(void) > +{ > + u32 reg; > + > + ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk); > + > + /* > + * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at > + * 8MHz, its derived from lp_apm. > + */ Is this true for all boards? I can imagine some boards are different. > + reg = __raw_readl(MXC_CCM_CBCDR); > + reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK; > + reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK; > + reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK; > + reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET); > + __raw_writel(reg, MXC_CCM_CBCDR); > + > + /* set parent for pll1, pll2 and pll3 */ > + pll1_main_clk.parent = &osc_clk; > + pll2_sw_clk.parent = &osc_clk; > + pll3_sw_clk.parent = &osc_clk; > + > + /* set ipg_perclk parent */ > + ipg_perclk.parent = &lp_apm_clk; > + reg = __raw_readl(MXC_CCM_CBCMR); > + if ((reg & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) != 0) { > + ipg_perclk.parent = &ipg_clk; > + } else { > + if ((reg & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL) == 0) > + ipg_perclk.parent = &main_bus_clk; > + } > +} > + > +int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2) > +{ > + struct clk **clkp; > + int i; > + > + external_low_reference = ckil; > + external_high_reference = ckih1; > + ckih2_reference = ckih2; > + oscillator_reference = osc; > + > + for (i = 0; i < ARRAY_SIZE(lookups); i++) > + clkdev_add(&lookups[i]); > + > + clk_tree_init(); > + > + clk_enable(&cpu_clk); > + clk_enable(&main_bus_clk); > + > + /* System timer */ > + mxc_timer_init(&gpt_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT); > + return 0; > +} > + > diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c > new file mode 100644 > index 0000000..65f9e5b > --- /dev/null > +++ b/arch/arm/mach-mx5/cpu.c > @@ -0,0 +1,46 @@ > +/* > + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. > + */ > + > +/* > + * The code contained herein is licensed under the GNU General Public > + * License. You may obtain a copy of the GNU General Public License > + * Version 2 or later at the following locations: > + * > + * http://www.opensource.org/licenses/gpl-license.html > + * http://www.gnu.org/copyleft/gpl.html > + * > + * This file contains the CPU initialization code. > + */ > + > +#include <linux/types.h> > +#include <linux/kernel.h> > +#include <linux/init.h> > +#include <mach/hardware.h> > +#include <asm/io.h> > + > +static int __init post_cpu_init(void) > +{ > + unsigned int reg; > + void __iomem *base; > + > + base = IO_ADDRESS(AIPS1_BASE_ADDR); > + __raw_writel(0x0, base + 0x40); > + __raw_writel(0x0, base + 0x44); > + __raw_writel(0x0, base + 0x48); > + __raw_writel(0x0, base + 0x4C); > + reg = __raw_readl(base + 0x50) & 0x00FFFFFF; > + __raw_writel(reg, base + 0x50); > + > + base = IO_ADDRESS(AIPS2_BASE_ADDR); > + __raw_writel(0x0, base + 0x40); > + __raw_writel(0x0, base + 0x44); > + __raw_writel(0x0, base + 0x48); > + __raw_writel(0x0, base + 0x4C); > + reg = __raw_readl(base + 0x50) & 0x00FFFFFF; > + __raw_writel(reg, base + 0x50); > + > + return 0; > +} > + > +postcore_initcall(post_cpu_init); This initcall should be protected with a cpu_is_mx51() > diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h > new file mode 100644 > index 0000000..590e31e > --- /dev/null > +++ b/arch/arm/mach-mx5/crm_regs.h > @@ -0,0 +1,685 @@ > +/* > + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. > + */ > + > +/* > + * The code contained herein is licensed under the GNU General Public > + * License. You may obtain a copy of the GNU General Public License > + * Version 2 or later at the following locations: > + * > + * http://www.opensource.org/licenses/gpl-license.html > + * http://www.gnu.org/copyleft/gpl.html > + */ > +#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ > +#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ > + > +#define MXC_CCM_BASE ((char *)IO_ADDRESS(CCM_BASE_ADDR)) > +#define MXC_DPLL1_BASE IO_ADDRESS(PLL1_BASE_ADDR) > +#define MXC_DPLL2_BASE IO_ADDRESS(PLL2_BASE_ADDR) > +#define MXC_DPLL3_BASE IO_ADDRESS(PLL3_BASE_ADDR) > + > +/* PLL Register Offsets */ > +#define MXC_PLL_DP_CTL 0x00 > +#define MXC_PLL_DP_CONFIG 0x04 > +#define MXC_PLL_DP_OP 0x08 > +#define MXC_PLL_DP_MFD 0x0C > +#define MXC_PLL_DP_MFN 0x10 > +#define MXC_PLL_DP_MFNMINUS 0x14 > +#define MXC_PLL_DP_MFNPLUS 0x18 > +#define MXC_PLL_DP_HFS_OP 0x1C > +#define MXC_PLL_DP_HFS_MFD 0x20 > +#define MXC_PLL_DP_HFS_MFN 0x24 > +#define MXC_PLL_DP_MFN_TOGC 0x28 > +#define MXC_PLL_DP_DESTAT 0x2c > + > +/* PLL Register Bit definitions */ > +#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000 > +#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 > +#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12 > +#define MXC_PLL_DP_CTL_ADE 0x800 > +#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 > +#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) > +#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 > +#define MXC_PLL_DP_CTL_HFSM 0x80 > +#define MXC_PLL_DP_CTL_PRE 0x40 > +#define MXC_PLL_DP_CTL_UPEN 0x20 > +#define MXC_PLL_DP_CTL_RST 0x10 > +#define MXC_PLL_DP_CTL_RCP 0x8 > +#define MXC_PLL_DP_CTL_PLM 0x4 > +#define MXC_PLL_DP_CTL_BRM0 0x2 > +#define MXC_PLL_DP_CTL_LRF 0x1 > + > +#define MXC_PLL_DP_CONFIG_BIST 0x8 > +#define MXC_PLL_DP_CONFIG_SJC_CE 0x4 > +#define MXC_PLL_DP_CONFIG_AREN 0x2 > +#define MXC_PLL_DP_CONFIG_LDREQ 0x1 > + > +#define MXC_PLL_DP_OP_MFI_OFFSET 4 > +#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4) > +#define MXC_PLL_DP_OP_PDF_OFFSET 0 > +#define MXC_PLL_DP_OP_PDF_MASK 0xF > + > +#define MXC_PLL_DP_MFD_OFFSET 0 > +#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF > + > +#define MXC_PLL_DP_MFN_OFFSET 0x0 > +#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF > + > +#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) > +#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) > +#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 > +#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF > + > +#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) > +#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF > + > +/* Register addresses of CCM*/ > +#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00) > +#define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04) > +#define MXC_CCM_CSR (MXC_CCM_BASE + 0x08) > +#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C) > +#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10) > +#define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14) > +#define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18) > +#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C) > +#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20) > +#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24) > +#define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28) > +#define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C) > +#define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30) > +#define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34) > +#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38) > +#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C) > +#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40) > +#define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44) > +#define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48) > +#define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C) > +#define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50) > +#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54) > +#define MXC_CCM_CISR (MXC_CCM_BASE + 0x58) > +#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C) > +#define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60) > +#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64) > +#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68) > +#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C) > +#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70) > +#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74) > +#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78) > +#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C) > +#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80) > +#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x84) > + > +/* Define the bits in register CCR */ > +#define MXC_CCM_CCR_COSC_EN (1 << 12) > +#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11) > +#define MXC_CCM_CCR_CAMP2_EN (1 << 10) > +#define MXC_CCM_CCR_CAMP1_EN (1 << 9) > +#define MXC_CCM_CCR_FPM_EN (1 << 8) > +#define MXC_CCM_CCR_OSCNT_OFFSET (0) > +#define MXC_CCM_CCR_OSCNT_MASK (0xFF) > + > +/* Define the bits in register CCDR */ > +#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18) > +#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) > +#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16) > + > +/* Define the bits in register CSR */ > +#define MXC_CCM_CSR_COSR_READY (1 << 5) > +#define MXC_CCM_CSR_LVS_VALUE (1 << 4) > +#define MXC_CCM_CSR_CAMP2_READY (1 << 3) > +#define MXC_CCM_CSR_CAMP1_READY (1 << 2) > +#define MXC_CCM_CSR_FPM_READY (1 << 1) > +#define MXC_CCM_CSR_REF_EN_B (1 << 0) > + > +/* Define the bits in register CCSR */ > +#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9) > +#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7) > +#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) > +#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5) > +#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5) > +#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3) > +#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3) > +#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) > +#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) > +#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) > + > +/* Define the bits in register CACRR */ > +#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0) > +#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7) > + > +/* Define the bits in register CBCDR */ > +#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) > +#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) > +#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30) > +#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30) > +#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27) > +#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) > +#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22) > +#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) > +#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19) > +#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) > +#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16) > +#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) > +#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13) > +#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) > +#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10) > +#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) > +#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8) > +#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) > +#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6) > +#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) > +#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3) > +#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) > +#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0) > +#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7) > + > +/* Define the bits in register CBCMR */ > +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14) > +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) > +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12) > +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) > +#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10) > +#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) > +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8) > +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) > +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6) > +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) > +#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4) > +#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) > +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14) > +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14) > +#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) > +#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) > + > +/* Define the bits in register CSCMR1 */ > +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30) > +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) > +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28) > +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) > +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26) > +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) > +#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24) > +#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) > +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22) > +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) > +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) > +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) > +#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) > +#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) > +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) > +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) > +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) > +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) > +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) > +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) > +#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) > +#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) > +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8) > +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) > +#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) > +#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) > +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4) > +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) > +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2) > +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) > +#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) > +#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1) > + > +/* Define the bits in register CSCMR2 */ > +#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3) > +#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3)) > +#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24) > +#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24) > +#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22) > +#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22) > +#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20) > +#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20) > +#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18) > +#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18) > +#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16) > +#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16) > +#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14) > +#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14) > +#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12) > +#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12) > +#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10) > +#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10) > +#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9) > +#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6) > +#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6) > +#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5) > +#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4) > +#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2) > +#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2) > +#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0) > +#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3) > + > +/* Define the bits in register CSCDR1 */ > +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22) > +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) > +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) > +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) > +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) > +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) > +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) > +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) > +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11) > +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) > +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8) > +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) > +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6) > +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) > +#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3) > +#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) > +#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0) > +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7) > + > +/* Define the bits in register CS1CDR and CS2CDR */ > +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22) > +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22) > +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16) > +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16) > +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6) > +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) > +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0) > +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F) > + > +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22) > +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22) > +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16) > +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16) > +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6) > +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) > +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0) > +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F) > + > +/* Define the bits in register CDCDR */ > +#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28) > +#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28) > +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25) > +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) > +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19) > +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19) > +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16) > +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16) > +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9) > +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9) > +#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6) > +#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6) > +#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3) > +#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3) > +#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0) > +#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7) > + > +/* Define the bits in register CHSCCDR */ > +#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12) > +#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12) > +#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6) > +#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6) > +#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3) > +#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3) > +#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0) > +#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7) > + > +/* Define the bits in register CSCDR2 */ > +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25) > +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) > +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19) > +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) > +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16) > +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) > +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9) > +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) > +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6) > +#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) > +#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0) > +#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F) > + > +/* Define the bits in register CSCDR3 */ > +#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16) > +#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16) > +#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9) > +#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9) > +#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6) > +#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6) > +#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0) > +#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F) > + > +/* Define the bits in register CSCDR4 */ > +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16) > +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16) > +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9) > +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9) > +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6) > +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6) > +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0) > +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F) > + > +/* Define the bits in register CDHIPR */ > +#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) > +#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8) > +#define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7) > +#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6) > +#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) > +#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4) > +#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3) > +#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2) > +#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1) > +#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0) > + > +/* Define the bits in register CDCR */ > +#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2) > +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0) > +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3) > + > +/* Define the bits in register CLPCR */ > +#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23) > +#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) > +#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) > +#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) > +#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) > +#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) > +#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17) > +#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16) > +#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11) > +#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9) > +#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) > +#define MXC_CCM_CLPCR_VSTBY (0x1 << 8) > +#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7) > +#define MXC_CCM_CLPCR_SBYOS (0x1 << 6) > +#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) > +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3) > +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) > +#define MXC_CCM_CLPCR_LPM_OFFSET (0) > +#define MXC_CCM_CLPCR_LPM_MASK (0x3) > + > +/* Define the bits in register CISR */ > +#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25) > +#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) > +#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20) > +#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19) > +#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18) > +#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17) > +#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16) > +#define MXC_CCM_CISR_COSC_READY (0x1 << 6) > +#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5) > +#define MXC_CCM_CISR_CKIH_READY (0x1 << 4) > +#define MXC_CCM_CISR_FPM_READY (0x1 << 3) > +#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2) > +#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1) > +#define MXC_CCM_CISR_LRF_PLL1 (0x1) > + > +/* Define the bits in register CIMR */ > +#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25) > +#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) > +#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20) > +#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19) > +#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18) > +#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17) > +#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16) > +#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5) > +#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4) > +#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3) > +#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2) > +#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1) > +#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1) > + > +/* Define the bits in register CCOSR */ > +#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24) > +#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21) > +#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) > +#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16) > +#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) > +#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) > +#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4) > +#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) > +#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0) > +#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF) > + > +/* Define the bits in registers CGPR */ > +#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4) > +#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3) > +#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0) > +#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7) > + > +/* Define the bits in registers CCGRx */ > +#define MXC_CCM_CCGR_CG_MASK 0x3 > +#define MXC_CCM_CCGR_MOD_OFF 0x0 > +#define MXC_CCM_CCGR_MOD_ON 0x3 > +#define MXC_CCM_CCGR_MOD_IDLE 0x1 > + > +#define MXC_CCM_CCGR0_CG15_OFFSET 30 > +#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30) > +#define MXC_CCM_CCGR0_CG14_OFFSET 28 > +#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28) > +#define MXC_CCM_CCGR0_CG13_OFFSET 26 > +#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26) > +#define MXC_CCM_CCGR0_CG12_OFFSET 24 > +#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24) > +#define MXC_CCM_CCGR0_CG11_OFFSET 22 > +#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22) > +#define MXC_CCM_CCGR0_CG10_OFFSET 20 > +#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20) > +#define MXC_CCM_CCGR0_CG9_OFFSET 18 > +#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18) > +#define MXC_CCM_CCGR0_CG8_OFFSET 16 > +#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16) > +#define MXC_CCM_CCGR0_CG7_OFFSET 14 > +#define MXC_CCM_CCGR0_CG6_OFFSET 12 > +#define MXC_CCM_CCGR0_CG5_OFFSET 10 > +#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10) > +#define MXC_CCM_CCGR0_CG4_OFFSET 8 > +#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8) > +#define MXC_CCM_CCGR0_CG3_OFFSET 6 > +#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6) > +#define MXC_CCM_CCGR0_CG2_OFFSET 4 > +#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4) > +#define MXC_CCM_CCGR0_CG1_OFFSET 2 > +#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2) > +#define MXC_CCM_CCGR0_CG0_OFFSET 0 > +#define MXC_CCM_CCGR0_CG0_MASK 0x3 > + > +#define MXC_CCM_CCGR1_CG15_OFFSET 30 > +#define MXC_CCM_CCGR1_CG14_OFFSET 28 > +#define MXC_CCM_CCGR1_CG13_OFFSET 26 > +#define MXC_CCM_CCGR1_CG12_OFFSET 24 > +#define MXC_CCM_CCGR1_CG11_OFFSET 22 > +#define MXC_CCM_CCGR1_CG10_OFFSET 20 > +#define MXC_CCM_CCGR1_CG9_OFFSET 18 > +#define MXC_CCM_CCGR1_CG8_OFFSET 16 > +#define MXC_CCM_CCGR1_CG7_OFFSET 14 > +#define MXC_CCM_CCGR1_CG6_OFFSET 12 > +#define MXC_CCM_CCGR1_CG5_OFFSET 10 > +#define MXC_CCM_CCGR1_CG4_OFFSET 8 > +#define MXC_CCM_CCGR1_CG3_OFFSET 6 > +#define MXC_CCM_CCGR1_CG2_OFFSET 4 > +#define MXC_CCM_CCGR1_CG1_OFFSET 2 > +#define MXC_CCM_CCGR1_CG0_OFFSET 0 > + > +#define MXC_CCM_CCGR2_CG15_OFFSET 30 > +#define MXC_CCM_CCGR2_CG14_OFFSET 28 > +#define MXC_CCM_CCGR2_CG13_OFFSET 26 > +#define MXC_CCM_CCGR2_CG12_OFFSET 24 > +#define MXC_CCM_CCGR2_CG11_OFFSET 22 > +#define MXC_CCM_CCGR2_CG10_OFFSET 20 > +#define MXC_CCM_CCGR2_CG9_OFFSET 18 > +#define MXC_CCM_CCGR2_CG8_OFFSET 16 > +#define MXC_CCM_CCGR2_CG7_OFFSET 14 > +#define MXC_CCM_CCGR2_CG6_OFFSET 12 > +#define MXC_CCM_CCGR2_CG5_OFFSET 10 > +#define MXC_CCM_CCGR2_CG4_OFFSET 8 > +#define MXC_CCM_CCGR2_CG3_OFFSET 6 > +#define MXC_CCM_CCGR2_CG2_OFFSET 4 > +#define MXC_CCM_CCGR2_CG1_OFFSET 2 > +#define MXC_CCM_CCGR2_CG0_OFFSET 0 > + > +#define MXC_CCM_CCGR3_CG15_OFFSET 30 > +#define MXC_CCM_CCGR3_CG14_OFFSET 28 > +#define MXC_CCM_CCGR3_CG13_OFFSET 26 > +#define MXC_CCM_CCGR3_CG12_OFFSET 24 > +#define MXC_CCM_CCGR3_CG11_OFFSET 22 > +#define MXC_CCM_CCGR3_CG10_OFFSET 20 > +#define MXC_CCM_CCGR3_CG9_OFFSET 18 > +#define MXC_CCM_CCGR3_CG8_OFFSET 16 > +#define MXC_CCM_CCGR3_CG7_OFFSET 14 > +#define MXC_CCM_CCGR3_CG6_OFFSET 12 > +#define MXC_CCM_CCGR3_CG5_OFFSET 10 > +#define MXC_CCM_CCGR3_CG4_OFFSET 8 > +#define MXC_CCM_CCGR3_CG3_OFFSET 6 > +#define MXC_CCM_CCGR3_CG2_OFFSET 4 > +#define MXC_CCM_CCGR3_CG1_OFFSET 2 > +#define MXC_CCM_CCGR3_CG0_OFFSET 0 > + > +#define MXC_CCM_CCGR4_CG15_OFFSET 30 > +#define MXC_CCM_CCGR4_CG14_OFFSET 28 > +#define MXC_CCM_CCGR4_CG13_OFFSET 26 > +#define MXC_CCM_CCGR4_CG12_OFFSET 24 > +#define MXC_CCM_CCGR4_CG11_OFFSET 22 > +#define MXC_CCM_CCGR4_CG10_OFFSET 20 > +#define MXC_CCM_CCGR4_CG9_OFFSET 18 > +#define MXC_CCM_CCGR4_CG8_OFFSET 16 > +#define MXC_CCM_CCGR4_CG7_OFFSET 14 > +#define MXC_CCM_CCGR4_CG6_OFFSET 12 > +#define MXC_CCM_CCGR4_CG5_OFFSET 10 > +#define MXC_CCM_CCGR4_CG4_OFFSET 8 > +#define MXC_CCM_CCGR4_CG3_OFFSET 6 > +#define MXC_CCM_CCGR4_CG2_OFFSET 4 > +#define MXC_CCM_CCGR4_CG1_OFFSET 2 > +#define MXC_CCM_CCGR4_CG0_OFFSET 0 > + > +#define MXC_CCM_CCGR5_CG15_OFFSET 30 > +#define MXC_CCM_CCGR5_CG14_OFFSET 28 > +#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28) > +#define MXC_CCM_CCGR5_CG13_OFFSET 26 > +#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26) > +#define MXC_CCM_CCGR5_CG12_OFFSET 24 > +#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24) > +#define MXC_CCM_CCGR5_CG11_OFFSET 22 > +#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22) > +#define MXC_CCM_CCGR5_CG10_OFFSET 20 > +#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20) > +#define MXC_CCM_CCGR5_CG9_OFFSET 18 > +#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18) > +#define MXC_CCM_CCGR5_CG8_OFFSET 16 > +#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16) > +#define MXC_CCM_CCGR5_CG7_OFFSET 14 > +#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14) > +#define MXC_CCM_CCGR5_CG6_OFFSET 12 > +#define MXC_CCM_CCGR5_CG5_OFFSET 10 > +#define MXC_CCM_CCGR5_CG4_OFFSET 8 > +#define MXC_CCM_CCGR5_CG3_OFFSET 6 > +#define MXC_CCM_CCGR5_CG2_OFFSET 4 > +#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4) > +#define MXC_CCM_CCGR5_CG1_OFFSET 2 > +#define MXC_CCM_CCGR5_CG0_OFFSET 0 > +#define MXC_CCM_CCGR6_CG7_OFFSET 14 > +#define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14) > +#define MXC_CCM_CCGR6_CG6_OFFSET 12 > +#define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12) > +#define MXC_CCM_CCGR6_CG5_OFFSET 10 > +#define MXC_CCM_CCGR6_CG5_MASK (0x3 << 10) > +#define MXC_CCM_CCGR6_CG4_OFFSET 8 > +#define MXC_CCM_CCGR6_CG4_MASK (0x3 << 8) > +#define MXC_CCM_CCGR6_CG3_OFFSET 6 > +#define MXC_CCM_CCGR6_CG2_OFFSET 4 > +#define MXC_CCM_CCGR6_CG1_OFFSET 2 > +#define MXC_CCM_CCGR6_CG0_OFFSET 0 > + > +#define MXC_CORTEXA8_BASE IO_ADDRESS(ARM_BASE_ADDR) > +#define MXC_GPC_BASE IO_ADDRESS(GPC_BASE_ADDR) > +#define MXC_DPTC_LP_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x80) > +#define MXC_DPTC_GP_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x100) > +#define MXC_DVFS_CORE_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x180) > +#define MXC_DPTC_PER_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x1C0) > +#define MXC_PGC_IPU_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x220) > +#define MXC_PGC_VPU_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x240) > +#define MXC_PGC_GPU_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x260) > +#define MXC_SRPG_NEON_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x280) > +#define MXC_SRPG_ARM_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x2A0) > +#define MXC_SRPG_EMPGC0_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x2C0) > +#define MXC_SRPG_EMPGC1_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x2D0) > +#define MXC_SRPG_MEGAMIX_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x2E0) > +#define MXC_SRPG_EMI_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x300) > + > +/* CORTEXA8 platform */ > +#define MXC_CORTEXA8_PLAT_PVID (MXC_CORTEXA8_BASE + 0x0) > +#define MXC_CORTEXA8_PLAT_GPC (MXC_CORTEXA8_BASE + 0x4) > +#define MXC_CORTEXA8_PLAT_PIC (MXC_CORTEXA8_BASE + 0x8) > +#define MXC_CORTEXA8_PLAT_LPC (MXC_CORTEXA8_BASE + 0xC) > +#define MXC_CORTEXA8_PLAT_NEON_LPC (MXC_CORTEXA8_BASE + 0x10) > +#define MXC_CORTEXA8_PLAT_ICGC (MXC_CORTEXA8_BASE + 0x14) > +#define MXC_CORTEXA8_PLAT_AMC (MXC_CORTEXA8_BASE + 0x18) > +#define MXC_CORTEXA8_PLAT_NMC (MXC_CORTEXA8_BASE + 0x20) > +#define MXC_CORTEXA8_PLAT_NMS (MXC_CORTEXA8_BASE + 0x24) > + > +/* DVFS CORE */ > +#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) > +#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04) > +#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08) > +#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C) > +#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10) > +#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14) > +#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18) > +#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C) > +#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20) > +#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24) > +#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28) > +#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C) > +#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30) > +#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34) > +#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38) > +#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C) > +#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40) > + > +/* GPC */ > +#define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0) > +#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4) > +#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8) > +#define MXC_GPC_ALL_PU (MXC_GPC_BASE + 0xC) > +#define MXC_GPC_NEON (MXC_GPC_BASE + 0x10) > +#define MXC_GPC_PGR_ARMPG_OFFSET 8 > +#define MXC_GPC_PGR_ARMPG_MASK (3 << 8) > + > +/* PGC */ > +#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0) > +#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC) > +#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0) > +#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC) > +#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0) > +#define MXC_PGC_GPU_PGSR (MXC_
From: Sascha Hauer on 4 Dec 2009 06:10 On Fri, Dec 04, 2009 at 04:47:05AM +0200, Amit Kucheria wrote: > Add basic clock support, cpu identification, I/O mapping and serial port. Boot > tested on Freescale Babbage 2.5 board. Can you split this into two patches, one for the i.MX51 support and one for the babbage board? Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo(a)vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
From: Russell King - ARM Linux on 10 Dec 2009 05:40 On Fri, Dec 04, 2009 at 04:47:05AM +0200, Amit Kucheria wrote: > +#include <linux/init.h> > +#include <linux/platform_device.h> > +#include <mach/common.h> > +#include <mach/hardware.h> > +#include <asm/irq.h> > +#include <asm/setup.h> > +#include <asm/mach-types.h> > +#include <asm/mach/arch.h> > +#include <asm/mach/time.h> > +#include <mach/memory.h> No one should be including mach/memory.h. Please remove it and find a better include to use. (mach/memory.h exists to provide asm/memory.h with the platform specific bits it needs, so maybe asm/memory.h is what you want here). > +#define SPIN_DELAY 1000000 /* in nanoseconds */ That's 1ms. > + /* Wait for lock */ > + getnstimeofday(&nstimeofday); > + while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF)) { > + getnstimeofday(&curtime); I doubt getnstimeofday is particularly light-weight, so I'm not sure what you're gaining over a loop based around udelay() and counting the iterations. > + if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY) > + panic("pll relock failed\n"); Is a panic really justified? > diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c > new file mode 100644 > index 0000000..b258917 > --- /dev/null > +++ b/arch/arm/mach-mx5/mm.c > @@ -0,0 +1,86 @@ > +/* > + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. > + * > + * The code contained herein is licensed under the GNU General Public > + * License. You may obtain a copy of the GNU General Public License > + * Version 2 or later at the following locations: > + * > + * http://www.opensource.org/licenses/gpl-license.html > + * http://www.gnu.org/copyleft/gpl.html > + * > + * Create static mapping between physical to virtual memory. > + */ > + > +#include <linux/mm.h> > +#include <linux/init.h> > +#include <mach/hardware.h> > +#include <asm/pgtable.h> I don't see anything needing asm/pgtable.h in here. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo(a)vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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