oprofile, perf, x86: introduce new functions to reserve perfctrs by index
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From: Robert Richter on 25 Mar 2010 12:00 Andi, so far it does not seem this reservation patches will go upstream. So we still do not have a solution of how to share the pmu with perf. The current approach is a global pmu lock. I don't think this is a good solution and we already see questions on the oprofile mailing list why counters are not available to use. This will become much worse if perf is using counters permanently in the kernel (e.g. the perf nmi watchdog). This will make oprofile unusable. On 20.03.10 06:45:44, Andi Kleen wrote: > Robert Richter <robert.richter(a)amd.com> writes: > > > Current perfctr reservation code allocates single pmu msrs. The msr > > addresses may differ depending on the model and offset calculation is > > necessary. This can be easier implemented by reserving a counter by > > its index only. > > Sorry reviewing old patch. This doesn't work for the fixed counters on intel, > which don't have a index (or rather they have a separate number space) > > I had a old patch to fix the reservation for them (and a matching > patch to perf to use it). > > How to resolve this? Fixed counter reservation is not really used in the kernel except for p4. Oprofile only reserves generic counters. Unless there is a general solution how to reserve counters I don't see the need to extend the reservation code for fixed counters since the only subsystem using it would be the nmi watchdog. -Robert -- Advanced Micro Devices, Inc. Operating System Research Center email: robert.richter(a)amd.com -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo(a)vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ |