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From: salimbaba on 24 Mar 2010 05:28
i am using spartan 3e board to transmit UDP packets to my pc. I can write
to PHY registers i.e. i have only done soft reset by writing 1 to 15th bit
of control register and i can see that it executes.

The problem is i cannot read the registers or at least i cannot see any
data in chipscope pro.

kindly help me out.

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From: salimbaba on 24 Mar 2010 06:53
//=========================================================================

module mdio_module(mdc,mdio,reset,clk,execute,req1,data_sta,sta_enb);
//-----------------------------------
output mdc;
inout mdio;

//-----------------------------------
input reset,clk;
input execute,req1; //


//-----------------------------------
output [15:0] data_sta;
output sta_enb;

//-----------------------------------
reg req,execute_reg;
reg [4:0] phy_addr,reg_addr;
reg [15:0] data_phy;
wire req_enb,mdio_in;
reg mdio_out;

//-----------------------------------
reg sta_enb;
reg state_z,z_reg; //
reg [2:0] state,state_d;
reg [4:0] count_bit,count_bit_d;
reg [15:0] data_sta;
reg change_enb; //
reg data;
//-------------------------------------
parameter phy_addr1 = 5'b11111;
parameter reg_addr1 = 5'b00000;
parameter data_phy1 = 16'b1000_0000_0000_0000;



//--------------------------------------
parameter IDLE_STATE=3'd0,PRE_STATE=3'd1,ST_STATE=3'd2,OP_STATE=3'd3,
PHYAD_STATE=3'd4,REGAD_STATE=3'd5,TA_STATE=3'D6,DATA_STATE=3'd7;

//------------------------------------------
assign mdc=clk;

//------------------------------------------
always @(posedge clk)
execute_reg<=execute;

assign req_enb=execute_reg&&(!execute);

always @(posedge reset or posedge clk)
if(reset) {req,phy_addr,reg_addr,data_phy}<=0;
else if(req_enb)
{req,phy_addr,reg_addr,data_phy}<={req1,phy_addr1,reg_addr1,data_phy1};

//------------------------------------------
assign mdio=(z_reg) ? 1'bz : mdio_out;
assign mdio_in=mdio;

//==========================================
always @(state or count_bit or IDLE_STATE or req_enb)
if(count_bit==0)
begin
if(state!=IDLE_STATE) change_enb=1;
else if(req_enb) change_enb=1; //
else change_enb=0;
end
else change_enb=0;

//----------------------------------------
always @(posedge clk or posedge reset)
if(reset) state<=IDLE_STATE;
else if(change_enb)
case(state)
IDLE_STATE: state<=PRE_STATE;
PRE_STATE: state<=ST_STATE;
ST_STATE: state<=OP_STATE;
OP_STATE: state<=PHYAD_STATE;
PHYAD_STATE: state<=REGAD_STATE;
REGAD_STATE: state<=TA_STATE;
TA_STATE: state<=DATA_STATE;
DATA_STATE: state<=IDLE_STATE;
default: state<=IDLE_STATE;
endcase

//-----------------------------------------
always @(posedge reset or posedge clk)
if(reset) count_bit<=0;
else if(change_enb)
case(state)
IDLE_STATE: count_bit<=31;
PRE_STATE: count_bit<=1;
ST_STATE: count_bit<=1;
OP_STATE: count_bit<=4;
PHYAD_STATE: count_bit<=4;
REGAD_STATE: count_bit<=1;
TA_STATE: count_bit<=15;
DATA_STATE: count_bit<=0;
default: count_bit<=0;
endcase
else if(count_bit!=0) count_bit<=count_bit-5'd1;

//----------------------------------------------
always @(posedge reset or posedge clk)
if(reset) data<=0;
else if(state==PRE_STATE) data<=1; //pre
else if(state==ST_STATE) //st
begin
if(count_bit==1) data<=0;
else data<=1;
end
else if(state==OP_STATE) //op
begin
if(count_bit==1) data<=(req) ? 1'b1 : 1'b0 ;
else data<=(req) ? 1'b0 : 1'b1 ;
end
else if(state==PHYAD_STATE) //phyad
data<=phy_addr[count_bit];
else if(state==REGAD_STATE) //regad
data<=reg_addr[count_bit];
else if(state==TA_STATE) //ta
begin
if(count_bit==1) data<=1'b1;
else data<=1'b0;
end
else if(state==DATA_STATE) //data
data<=data_phy[count_bit];

always @(negedge clk) mdio_out<=data;

//----------------------------------------------
always @(posedge reset or posedge clk)
if(reset) state_z<=1;
else if(state==IDLE_STATE) state_z<=1;
else if((state==DATA_STATE)&&req) state_z<=1;
else if((state==TA_STATE)&&req) state_z<=1;
else state_z<=0;

always @(negedge clk) z_reg<=state_z;
//--------------------------------------------------------
always @(posedge reset or posedge clk)
if(reset) data_sta<=16'd0;
else data_sta<={data_sta[14:0],mdio_in};

//--------------------------------------------------------
always @(posedge reset or posedge clk)
if(reset) sta_enb<=0;
else sta_enb<=((state_d==DATA_STATE)&&(count_bit_d==0)&&req);

always @(posedge clk)
{state_d,count_bit_d}<={state,count_bit};

endmodule



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