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From: H. Peter Anvin on 11 Jan 2010 19:20
On 01/11/2010 04:06 PM, Suresh Siddha wrote:
>>
>> Yes, that's what I said. My question was to Suresh what enforces that
>> in the case of his patch, which moves the legacy range into the middle
>> of the device vectors.
>
> It's not the used_vector bitmap. That range will appear as used on all
> the cpu's and hence we won't be allocating it for anything else.
>

OK, fair enough.

> Now the question is: for non-legacy (io-apic) case, instead of reserving
> this range for all the cpu's, does it make sense to generalize like any
> other vector?

It sounds like something that we could experiment with -- after
switching an IRQ to ioapic mode, make it a movable interrupt. It
*seems* it should work, but it's scary stuff to muck with.

Eric, do you see any reason why it wouldn't work? I truly couldn't
understand your previous remark, especially the bit about "it is
dangerous to play lowest priority irq games in that range".

-hpa


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From: H. Peter Anvin on 11 Jan 2010 19:40
On 01/11/2010 04:28 PM, Eric W. Biederman wrote:
>
> Sorry. I suck at multitasking.
>
> Without changes assign_irq_vector will reuse vectors in the range
> IRQ0_VECTOR to IRQ15_VECTOR in the code as it we currently ship it,
> when we switch irq0-15 into ioapic mode.
>
> Switching the loop to cover IRQ0_VECTOR to IRQ15_VECTOR is not a
> problem. I don't think it will find anything free as we assign those
> vectors on all cpus, but the data structures are fine.
>
> I am uncomfortable with the suggestion of sharing the priority of the
> IRQ_MOVE_CLEANUP_VECTOR with other interrupts. I know if it had be
> clear from the documentation that it was safe to share the irq level
> with other interrupts I would not have reserved the entire interrupt
> level for the IRQ_MOVE_CLEANUP_VECTOR.
>

What are the properties that you're looking for, and in what
documentation? We reviewed the Software Development Manual here at
Intel, and it rather explicitly states:

"Each interrupt priority level (sometimes interpreted by software as an
interrupt priority class) encompasses 16 vectors. Prioritizing
interrupts within a priority level is determined by the vector number.
The higher the vector number, the higher the priority within that
priority level. In determining the priority of a vector and ranking
of vectors within a priority group, the vector number is often divided
into two parts, with the high 4 bits of the vector indicating its
priority and the low 4 bit indicating its ranking within the priority
group."

[Intel� 64 and IA-32 Architectures Software Developer�s Manual
Volume 3A: System Programming Guide, Part 1; September 2009, Order
Number 253668-032US; section 10.9.3, page 10-57f.]

So 0x20 is the lowest-priority vector within priority group 0x2.

-hpa
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From: H. Peter Anvin on 11 Jan 2010 19:50
On 01/11/2010 04:28 PM, Eric W. Biederman wrote:
>
> Without changes assign_irq_vector will reuse vectors in the range
> IRQ0_VECTOR to IRQ15_VECTOR in the code as it we currently ship it,
> when we switch irq0-15 into ioapic mode.
>
> Switching the loop to cover IRQ0_VECTOR to IRQ15_VECTOR is not a
> problem. I don't think it will find anything free as we assign those
> vectors on all cpus, but the data structures are fine.
>

The question there is if we can treat the resulting ioapic IRQs as
normal movable IRQs, and just let the target-moving mechanism take care
of it. After all, there is a discrete event at which we decide that any
particular interrupt is an IOAPIC interrupt instead of XT-PIC.
Obviously, the vectors that remain XT-PIC vectors have to remain
allocated on all vectors for all time.

Another question is why we reserve the legacy IRQ 2 vector at all --
except when ACPI is present! I don't think it could ever be tickled,
and it sort of felt as a "just in case" thing that could be removed.

-hpa
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From: H. Peter Anvin on 11 Jan 2010 21:20
On 01/11/2010 05:52 PM, Eric W. Biederman wrote:
>
> After having the documentation quoted at me. I am having a distinct
> memory of one piece of documentation saying:
> "interrupts within a priority level can be delivered in any order"
>
> So I am guessing there is not any ordering of interrupts in the same
> priority level until they get to the local apic.
>

There is no ordering of interrupts before they hit the local APIC, since
the local APIC is what would serialize them...

> What guarantee we need is the interesting question.
>
> The cleanup ipi is sent when we have seen an interrupt arrive at it's
> newly configured location. It is possible that there is still an
> interrupt in flight to the old configured location (think NUMA where
> the interrupt has been migrated from off node to on node). We want
> the guarantee that the ipi arrives after the inflight irq. Which
> means on the wire ordering as well as in the local apic ordering is
> interesting.

I don't think there is any such guarantee possible, but that that has
nothing to do with the interrupt priority. Suresh tells me that that is
handled by detecting and re-posting the migration IRQ.

> I am slammed with other stuff right now so I don't think I will have
> time to find the old documentation I was looking at for a couple of
> more days.

I'm wondering if what you're thinking of are the really old LAPICs which
could only remember two pending interrupts per priority level?

-hpa

--
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel. I don't speak on their behalf.

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From: H. Peter Anvin on 13 Jan 2010 15:50
On 01/13/2010 12:36 PM, Eric W. Biederman wrote:
> "H. Peter Anvin" <hpa(a)zytor.com> writes:
>
>> On 01/11/2010 05:52 PM, Eric W. Biederman wrote:
>>>
>>> After having the documentation quoted at me. I am having a distinct
>>> memory of one piece of documentation saying:
>>> "interrupts within a priority level can be delivered in any order"
>>>
>>> So I am guessing there is not any ordering of interrupts in the same
>>> priority level until they get to the local apic.
>>>
>>
>> There is no ordering of interrupts before they hit the local APIC, since
>> the local APIC is what would serialize them...
>
> The io apic serializes them, and sends them over either the 2-wire
> bus or the front side bus. How much serialization and prioritization
> happens at that point I am not certain, but some certainly happens
> before you get to the local apic.
>

If you *have* a front side bus, that is! With QPI or HyperTransport,
you don't have a single serializing bus in the same way, but you have a
mesh network instead.

-hpa

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