12 and 16-bit oscilloscopes
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From: Joel Kolstad on 18 Dec 2006 13:44 "John Devereux" <jdREMOVE(a)THISdevereux.me.uk> wrote in message news:87d56hkrd9.fsf(a)cordelia.devereux.me.uk... > I would love to make a "scope" based on something like the > AD7660. It's a 24 bit 2.5MHz sigma delta ADC > - PC does post processing for "triggering", averaging, spectrum analysis Probably a handy option, but having a PC sift through 2.5MSps just looking for an edge to trigger on seems like a bit of a waste of the CPU. With some programmable logic (CPLD/FPGA) in the same box as the ADC, you could perform triggering there and then be able to use much lower-end PCs.
From: John Devereux on 18 Dec 2006 14:48 "Joel Kolstad" <JKolstad71HatesSpam(a)yahoo.com> writes: > "John Devereux" <jdREMOVE(a)THISdevereux.me.uk> wrote in message > news:87d56hkrd9.fsf(a)cordelia.devereux.me.uk... >> I would love to make a "scope" based on something like the >> AD7660. It's a 24 bit 2.5MHz sigma delta ADC >> - PC does post processing for "triggering", averaging, spectrum analysis > > Probably a handy option, but having a PC sift through 2.5MSps just > looking for an edge to trigger on seems like a bit of a waste of the > CPU. With some programmable logic (CPLD/FPGA) in the same box as > the ADC, you could perform triggering there and then be able to use > much lower-end PCs. Probably - I have not really looked at the numbers too seriously. But desktop CPUs are *very* fast, and edge detection is pretty easy. It would already be doing signal averaging and maybe digital filtering (especially on the slower "timebases"). So simple level detection would not be much extra work. Of course we could do all this in a bigger FPGA, but then where do you stop... -- John Devereux
From: Mike Monett on 18 Dec 2006 18:54 John Devereux <jdREMOVE(a)THISdevereux.me.uk> wrote: > "Joel Kolstad" <JKolstad71HatesSpam(a)yahoo.com> writes: >> "John Devereux" <jdREMOVE(a)THISdevereux.me.uk> wrote in message >> news:87d56hkrd9.fsf(a)cordelia.devereux.me.uk. >>> I would love to make a "scope" based on something like the >>> AD7660. It's a 24 bit 2.5MHz sigma delta ADC PC does post >>> processing for "triggering", averaging, spectrum analysis >> Probably a handy option, but having a PC sift through 2.5MSps >> just looking for an edge to trigger on seems like a bit of a >> waste of the CPU. With some programmable logic (CPLD/FPGA) in the >> same box as the ADC, you could perform triggering there and then >> be able to use much lower-end PCs. > Probably - I have not really looked at the numbers too seriously. > But desktop CPUs are *very* fast, and edge detection is pretty > easy. It would already be doing signal averaging and maybe digital > filtering (especially on the slower "timebases"). So simple level > detection would not be much extra work. > Of course we could do all this in a bigger FPGA, but then where do > you stop. I regularly take one million or more samples with the Binary Sampler and search the waveforms for different characteristics. Even with smoothing, the response from the keyboard on a 466MHz cpu is almost instantaneous. You should have little trouble finding a desired starting point to display a waveform. The software is Borland Pascal using inline assembly for the critical sections. I run DOS in Flat Real Mode (FRM) and store the data in Extended Memory. FRM gives instant access to memory above 1 Meg without having to go through Himem, which is painfully slow. Doing the edge detect in software eliminates the problems with hardware triggering and the extra jitter it adds. I plan to use this technique for an inexpensive 5GHz Binary Sampling scope running on a pc. I was going to use the pc sound card to transfer the waveform, but it needs to have a response to DC. So a simple 16-bit ADC is probably the way to go. The AD7660 looks quite interesting. The 120dB SNR up to 78KHz is impressive. It might be a good compliment to the inherent noise-rejection capability of the Binary Sampler. This might produce an inexpensive scope with unique capability and wide bandwidth. Regards, Mike Monett Antiviral, Antibacterial Silver Solution: http://silversol.freewebpage.org/index.htm SPICE Analysis of Crystal Oscillators: http://silversol.freewebpage.org/spice/xtal/clapp.htm Noise-Rejecting Wideband Sampler: http://www3.sympatico.ca/add.automation/sampler/intro.htm
From: Joel Kolstad on 18 Dec 2006 19:12 Mike, "Mike Monett" <No(a)email.adr> wrote in message news:Xns989DC03017A9ANoemailadr(a)208.49.80.251... > I regularly take one million or more samples with the Binary Sampler > and search the waveforms for different characteristics. Even with > smoothing, the response from the keyboard on a 466MHz cpu is almost > instantaneous. .... > I run DOS in Flat Real Mode (FRM) and store the > data in Extended Memory. I'm impressed with what you're able to do, but you realize you've at least decimated your market by working on a product that requires *DOS*???!!! ---Joel
From: Tom Bruhns on 18 Dec 2006 21:06
Mike Monett wrote: > John Devereux <jdREMOVE(a)THISdevereux.me.uk> wrote: > > > "Joel Kolstad" <JKolstad71HatesSpam(a)yahoo.com> writes: > > >> "John Devereux" <jdREMOVE(a)THISdevereux.me.uk> wrote in message > >> news:87d56hkrd9.fsf(a)cordelia.devereux.me.uk. > > >>> I would love to make a "scope" based on something like the > >>> AD7660. It's a 24 bit 2.5MHz sigma delta ADC PC does post > >>> processing for "triggering", averaging, spectrum analysis > > >> Probably a handy option, but having a PC sift through 2.5MSps > >> just looking for an edge to trigger on seems like a bit of a > >> waste of the CPU. With some programmable logic (CPLD/FPGA) in the > >> same box as the ADC, you could perform triggering there and then > >> be able to use much lower-end PCs. > > > Probably - I have not really looked at the numbers too seriously. > > > But desktop CPUs are *very* fast, and edge detection is pretty > > easy. It would already be doing signal averaging and maybe digital > > filtering (especially on the slower "timebases"). So simple level > > detection would not be much extra work. > > > Of course we could do all this in a bigger FPGA, but then where do > > you stop. > > I regularly take one million or more samples with the Binary Sampler > and search the waveforms for different characteristics. Even with > smoothing, the response from the keyboard on a 466MHz cpu is almost > instantaneous. You should have little trouble finding a desired > starting point to display a waveform. > > The software is Borland Pascal using inline assembly for the > critical sections. I run DOS in Flat Real Mode (FRM) and store the > data in Extended Memory. FRM gives instant access to memory above 1 > Meg without having to go through Himem, which is painfully slow. > > Doing the edge detect in software eliminates the problems with > hardware triggering and the extra jitter it adds. I plan to use this > technique for an inexpensive 5GHz Binary Sampling scope running on a > pc. I was going to use the pc sound card to transfer the waveform, > but it needs to have a response to DC. So a simple 16-bit ADC is > probably the way to go. > > The AD7660 looks quite interesting. The 120dB SNR up to 78KHz is > impressive. It might be a good compliment to the inherent > noise-rejection capability of the Binary Sampler. This might produce > an inexpensive scope with unique capability and wide bandwidth. > .... Hi Mike, Joel and all, OK, the AD7660 is a 16-bit successive approximation ADC that's pretty decent. The AD7760 is the 24-bit delta-sigma part. I'm not quite seeing the 120dB SNR in the data sheet for the AD7760--looks like 112dB to me. At 78kHz bandwidth, that's about -160dBfs/Hz. That's good, certainly, though it's not all that different from a 130Ms/s part that has a 78dB SNR: such a part has a noise level at about -156dBfs/Hz. If it's really for a scope, my main interest in more bits would be to avoid input ranging, and that's not all that difficult at low frequencies (1MHz these days is "practically DC"...). But if it's for spectral analysis, that's a different story. Then distortion and noise are important (more important than the number of bits, which is largely a red herring). My personal interest would be in fewer bits and much faster sampling: maybe a Virtex 5 connected to two or four 500Ms/s converters, into a deep buffer memory. Cheers, Tom |