Prev: what happened CBM=VGA
Next: 1581 Drive Kits on eBay
From: Jim Brain on 19 May 2006 18:03 Eric Smith wrote: > Jim Brain <brain(a)jbrain.com> writes: >> I don't think a PLA allows X (don't care) states. > > Certainly it does. That's one of the primary distinguishing characteristics > of a PLA as opposed to a ROM. I'll defer. All I know is the DTV designer said she originally did not include any illops in the design because she could not emulate the wored-or matrix in the FPGA in a space efficient manner. I assumed the FPGA is a superset functionality of the PLA, and thus if it can't be easily dealt with with in there, I didn;t think it could in the PLA. Jim
From: Jim Brain on 19 May 2006 18:16 Michael J. Mahon wrote: > Not so. The logical elements of the NMOS design are not present in > the same form in CMOS. And the instruction decoding was clearly > redesigned, as was the control section (changed timings and bus cycle > patterns, new instructions). I guess we'll agree to disagree on the point. I say all the design elements are there (the 8 bit ALU, decimal mode, the 16 bit instruction pointer, etc.) As for the instruction decoding, Bill just cleaned up the don't cares, as I see it. Hardly a huge new design. The physical elements changed, yes, but the logical perspective stayed the same. When I interviewed him back in 1995, he said as much. He simply wanted to clean up the design and lay it out so he could take advantage of not only the CMOS process but the ability to shrink the feature size every so many years. He hasn;t changed his design since the original. He just shrinks the design using the newer process and re-fabs. That's how he stated he got his speed increases. > That kind of behavior is of a completely different kind than random > bus clashes as multiple data sources are unintentionally gated onto > a bus! I'll agree they are different, but the point was that they are both undocumented behavior. Intel found the undocumented behavior was used all over, so they had to build in support for it. Therefore, every new Intel CPU supports this "undocumented behavior". Of course, it is now documented, so it becomes legitimate by virtue of so many people exploiting it that it became the std. > Not the norm, I would say, but the *only* 6502 implementation ever > used on that platform. I'd say that it illustrates my original point. It probably does not qualify, but the C65 used a different implementation of the 02, and the CLCD used a CMOS '02 as well. > Long after the 65C02 design was available, lower power, faster, and > cheaper to make, the CBM line could not easily make use of it. If it had made economic sense, CBM would have tasked Mensch to add the errata into the C02. Apple got Bill to change the 816 timings, and CBM had more clout with Bill, since they originally helped set up WDC. But, I'll concede the point that it would have required more cash and time than the Apple II line needed. I guess, in priciple, I agree with you that undocs fly against the rule of programming. HOwever, in the CBM environment, the rules are a bit different. As well, regardless of how one views the use of undocs, I'm not willing to be harsh on the MOS folks for what they did. They made a $20 CPU and got Woz and the Bushnell interested in using CPUs, which brought all of us to where we are today. I won't let a few space and time saving details that made perfect since in the early 1970's cloud that. Jim
From: Eric Smith on 19 May 2006 18:50 Jim Brain wrote: > I don't think a PLA allows X (don't care) states. I wrote: > Certainly it does. That's one of the primary distinguishing > characteristics > of a PLA as opposed to a ROM. Jim Brain <brain(a)jbrain.com> writes: > I'll defer. All I know is the DTV designer said she originally did > not include any illops in the design because she could not emulate the > wored-or matrix in the FPGA in a space efficient manner. That's true. > I assumed the FPGA is a superset functionality of the PLA, and thus if it > can't be easily dealt with with in there, I didn;t think it could in the > PLA. There's a lot of difference between an FPGA being conceptually a superset of a PLA, and an FPGA being able to efficiently implement any particular PLA. I've been trying to cram the logic of the DEC J11 microprocessor into an FPGA, and the decode PLA in that, which is relatively small in the actual J11 chip, takes up an enormous amount of FPGA space. The problem is that an FPGA cell is much more coarse-grained than a PLA "cell", which is just a transistor. Eric
From: Eric Smith on 19 May 2006 18:57 Michael J. Mahon wrote: > Not so. The logical elements of the NMOS design are not present in > the same form in CMOS. And the instruction decoding was clearly > redesigned, as was the control section (changed timings and bus cycle > patterns, new instructions). Jim Brain <brain(a)jbrain.com> writes: > I guess we'll agree to disagree on the point. I say all the design > elements are there (the 8 bit ALU, decimal mode, the 16 bit > instruction pointer, etc.) As for the instruction decoding, Bill just > cleaned up the don't cares, as I see it. You're talking about two completely different design levels. Michael is talking about transistors, gates, PLAs, and flip-flops. You (Jim) are talking about the programmer-visible processor architecture. It's possible to produce two processors with vastly different implementations that have the same architecture, e.g., IBM System 360/30 versus System 360/67, which shared almost no commonality of hardware design, but could run the same software. It's also possible to produce two processors with nearly the same hardware implementation, but dramatically different architecture. The 65C02 architecture is almost a superset of the 6502. The implementation is *much* different. > Hardly a huge new design. Tell us that after you design a 6502 replacement in a new technology. > The physical elements changed, yes, but the logical perspective stayed > the same. When I interviewed him back in 1995, he said as much. The "physical elements changed" is basically stating that the entire chip was redesigned. We could build a very slow 6502-compatible processor out of a lot of tinkertoys, and still have the same "logical perspective". I don't think you'd try to claim that it wasn't a huge new design.
From: Matthew W. Miller on 19 May 2006 22:15
On 2006-05-19, heuser.marcus(a)freenet.de wrote: >> Some hungarian maniacs have reverse engineered the 6502: >> http://impulzus.sch.bme.hu/6502/6502/ >> Sadly the site is in hungarian language, but atleast the logic diagrams >> speak for themselves. > Maniacs indeed! Thanks for the link, John! > Now - does anybody know something equivalent for the Z80? Sure, here's one: http://www.ieee-virtual-museum.org/media/Y9pqVm6tdZqV.jpg -- Matthew W. Miller <mwmiller(a)columbus.rr.com> Om mani padme sum. |