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From: Weng Tianxiang on 6 Jan 2010 11:51
Hi Xilinx,
Here is the error reporting with its code and compilation result with
ISE 10.1 and service pack 3.
The code is specially simplified to highlight the VHDL compiler error
characteristics.
There are global data array definitions.
when one of many data in the global data array is accessed in one
logic level, all other non-accessed data in the global data array
cannot be accessed and declared a data access error.
I list only one error case when one of many data in the global data
array is accessed at one level.
Another similar error case is when one of many data in the global data
array is accessed at two different levels in a module, the same
compilation error occurs again.

Error reason: Each of many data in a global data array must have its
independent own data source ID and a global data array cannot share
only one data source ID to determine whether the access violation
occurs or not.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Package XILINX_ERROR_REPORT is
constant TOP : integer := 1;
constant BOTTOM : integer := 0;
signal Error : unsigned(TOP downto BOTTOM);
end package;

-------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.XILINX_ERROR_REPORT.all;

entity Xilinx_Error is
generic(X : integer := 1);
port(
CLK : in std_logic;
SINI : in std_logic;

Error_I : in std_logic;
Error_O : out std_logic
);
end Xilinx_Error;

architecture A of Xilinx_Error is
begin
Error_O <= Error(X);

A1 : process(CLK)
begin
if CLK'event and CLK = '1' then
if SINI = '1' then
Error(X) <= '0';
else
if Error_I = '1' then
Error(X) <= '1';
else
Error(X) <= '0';
end if;
end if;
end if;
end process;
end A;

-------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.XILINX_ERROR_REPORT.all;

entity Xilinx_Error_Detect is
generic(X : integer := 1);
port(
CLK : in std_logic;
SINI : in std_logic;
Error_I : in std_logic_vector(TOP downto BOTTOM);
Error_O : out std_logic_vector(TOP downto BOTTOM)
);
end Xilinx_Error_Detect;

architecture A of Xilinx_Error_Detect is
component Xilinx_Error is
generic(X : integer := 1);
port(
CLK : in std_logic;
SINI : in std_logic;
Error_I : in std_logic;
Error_O : out std_logic
);
end component;

begin
Generate_A : for J in BOTTOM to TOP generate
Xilinx_Error_A : Xilinx_Error
generic map(X => J)
port map (
CLK => CLK,
SINI => SINI,
Error_I => Error_I(J),
Error_O => Error_O(J)
);
end generate;
end A;

-------------------------------------------------------------------------------
==================================================
=======================
* HDL
Compilation *
==================================================
=======================
Compiling vhdl file "C:/Xilinx-Error-Report/Xilinx_Error_Report.vhd"
in Library work.
Package <xilinx_error_report> compiled.
Entity <xilinx_error> compiled.
Entity <xilinx_error> (Architecture <a>) compiled.
Entity <xilinx_error_detect> compiled.
Entity <Xilinx_Error_Detect> (Architecture <A>) compiled.

==================================================
=======================
* Design Hierarchy
Analysis *
==================================================
=======================
Analyzing hierarchy for entity <Xilinx_Error_Detect> in library <work>
(architecture <A>) with generics.
X = 1

Analyzing hierarchy for entity <Xilinx_Error> in library <work>
(architecture <a>) with generics.
X = 0

Analyzing hierarchy for entity <Xilinx_Error> in library <work>
(architecture <a>) with generics.
X = 1


==================================================
=======================
* HDL
Analysis *
==================================================
=======================
Analyzing generic Entity <Xilinx_Error_Detect> in library <work>
(Architecture <A>).
X = 1
Entity <Xilinx_Error_Detect> analyzed. Unit <Xilinx_Error_Detect>
generated.

Analyzing generic Entity <Xilinx_Error.1> in library <work>
(Architecture <a>).
X = 0
Entity <Xilinx_Error.1> analyzed. Unit <Xilinx_Error.1> generated.

Analyzing generic Entity <Xilinx_Error.2> in library <work>
(Architecture <a>).
X = 1
ERROR:Xst:2548 - "C:/Xilinx-Error-Report/Xilinx_Error_Report.vhd" line
36:
Signal 'Error' defined in a package is already used in entity
<Xilinx_Error.1>.
-->

Total memory usage is 129212 kilobytes

Number of errors : 1 ( 0 filtered)
Number of warnings : 1 ( 0 filtered)
Number of infos : 0 ( 0 filtered)


Process "Synthesis" failed

In the above example, Error(1 downto 0) is declared in package
XILINX_ERROR_REPORT, and its components are used in different modules:
Error(0) is used in module Xilinx_Error.1 and Error(1) is used in
module Xilinx_Error.2, but the compiler fails to correctly register
the domain for each of Error(1 downto 0) and declares a error that is
not an error.

Weng
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