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CoreTimer programming in Actel SoftConsole Hello, I am trying to measure the execution time of some code using a CoreTimer block connected to a Cortex-M1 processor design in an Actel Fusion part. My problem is that TMR_current_value() always returns 0. I am trying to run in TMR_ONE_SHOT_MODE but I have also tried continuous mode but no change. I ha... 13 Aug 2010 14:39
How to use VIO and core inserter at the same time. Hi, I'am seeking a way to use VIO and core inserter at the same time. I found that if I want to use VIO , I must also instantiating ILA. I feel it's awkward. Please help me find a better way.Thanks. --------------------------------------- Posted through http://www.FPGARelated.com ... 13 Aug 2010 17:56
XC5VTX240T-2FF1759I4177 Could someone please help me to identify the suffix, "4177", on this Virtex-5 device and what it calls out as well as the meaning? Could I use this device in replace of the XC5VTX240T-2FF1759I (Without 4177 suffix)? Avnet advertizes them both however the one with the "4177" suffix is roughly $1,000.00 more? It seem... 12 Aug 2010 23:31
Spartan3a: improving DCM performance and Phil, what board are you using? Cant you just swap the oscillator for a faster one? Jon --------------------------------------- Posted through http://www.FPGARelated.com ... 13 Aug 2010 20:08
Altera Sales Does anybody have an email address for Altera Sales in South East Asia ? All email to Altera and their distributors is not being answered. Thanks, rudi ... 12 Aug 2010 01:42
Annual ASIC Prototyping-Verification with FPGA Survey – Free summary and Amazon or Dangdang drawings Hi all. Our annual survey is now open for responses in both English and Chinese. Free survey summary of results and Amazon (or Dangdang) drawings for all who qualify. Deadline for completion is Aug 18th. Cheers. -- John -- Deadline extended to include global inputs -- Welcome to the Third Annual Chip Design ... 11 Aug 2010 14:43
DMA operation to 64-bits PC platform On Jul 6, 12:12 pm, Michael S <already5cho...(a)yahoo.com> wrote: On Jul 6, 11:00 am, Frank van Eijkelenburg <fei.technolut...(a)gmail.com> wrote: I hope to fix the problem before my vacation (only one day left :) Something, I most certainly DO NOT RECOMMEND for final solution, but it could help to g... 12 Aug 2010 14:45
Spartan3a: improving DCM performance and "To achieve optimal frequency synthesis performance..." warning On Aug 10, 8:43 pm, Philip Pemberton <usene...(a)philpem.me.uk> wrote: Hi guys, Can anyone explain the following INFO alert I saw in my ISE build log? INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp clock_gener... 11 Aug 2010 21:20
Spartan3a: improving DCM performance and "To achieve optimalfrequency synthesis performance..." warning Hi guys, Can anyone explain the following INFO alert I saw in my ISE build log? INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp clock_generator/DCM_SP_INST, consult the device Interactive Data Sheet. This is on a Sparta... 10 Aug 2010 22:25
Best clock output pin in Spartan-3 Same question. Does anybody know it? --- news://freenews.netfront.net/ - complaints: news(a)netfront.net --- ... 10 Aug 2010 20:13
Instantiating non-global clock buffers (Xilinx ISE) I have a design with too many global clocks which ISE automatically adds. Some of these clocks are slow and feed into relatively small areas of logic. Is there a way I can specify these clocks to be non-global? ... 11 Aug 2010 14:43
Multiple builds with different top-level generic Hi, I'm working on a Xilinx FPGA design (VHDL) that uses a top level generic, and need to build multiple versions of the FPGA where the generic is the only thing that changes. The generic is used to select different modules to be used in the FPGA, the modules can't all fit in the FPGA together. Currently... 10 Aug 2010 09:04
Signal value clears for no reason [VHDL, ISE 10.1] Hello, Well my code is huge... but the interesting part is.. lets say i have some 10 bit wide signal, and in my logic i clear it when it reaches value 768. Actually its not just signal, its a D flip-flop with a controlling mux, and i load new value or clear it using the Mux... When i was running and synthesizi... 10 Aug 2010 11:20
VHDL newbie- stuck just weeks before project submission :(..please help Hello, For my Masters project, I'm trying to implement a multiplier, and a MAC where the outputs are calculated per clock cycle and stored in a text file which can then be used for further processing. However, both these designs are giving out partial products(I guess they are partial products) at the output t... 10 Aug 2010 19:06
ICTP Regional Course on FPGA Design in South and Southeast Asia Dear Colleague, We are pleased to announce the First ICTP Regional Microelectronics Course on VHDL for Hardware Synthesis and FPGA Design in South and Southeast Asia, The Abdus Salam International Centre for Theoretical Physics (ICTP, Italy) along with the North South University (NSU, Bangladesh) will orga... 6 Aug 2010 07:08
xilinx usb cable which cypress tool is used to read or write the PID,VID in EEPROM in xilinx usb programmer? I want to read the PID,VID from xilinx spartan-3E starter kit how can i do that? --------------------------------------- Posted through http://www.FPGARelated.com ... 6 Aug 2010 07:08
Verification of the SEU estimates Hello All, I am writing this to seek your guidance in knowing the possible methods/procedures to verify the analytical SEU estmiates for an FPGA designs. To my understanding the way to go about it is beam testing or laser testing. The fault injection methods don't seem to me prudent in this case as we are checking ... 5 Aug 2010 15:45
Spartan 3AN Starter Kit. Sell. I'd like to sell my Xiling Spartan 3AN Starter Kit (almost new and full working). http://www.xilinx.com/products/devkits/HW-SPAR3AN-SK-UNI-G.htm If anyone interested contact me. Thank you. --------------------------------------- Posted through http://www.FPGARelated.com ... 5 Aug 2010 06:56
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