From: John Larkin on
On Fri, 11 Jun 2010 15:24:34 +0100, John Devereux
<john(a)devereux.me.uk> wrote:

>John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> writes:
>
>> On Thu, 10 Jun 2010 22:36:32 -0500, "krw(a)att.bizzzzzzzzzzzz"
>> <krw(a)att.bizzzzzzzzzzzz> wrote:
>>
>>
>>>>>>Here's the board.
>>>>>>
>>>>>>ftp://jjlarkin.lmi.net/V220.gif
>>>>>>
>>>>>>The 12 ARMs run down the middle. To their right are the data
>>>>>>isolators, regulators, jtag connector, and dc/dc converter. The analog
>>>>>>stuff is to the left.
>>>>>>
>>>>>>This is a 12-channel 4-20 mA sort of i/o board.
>>>>>
>>>>>How many I/O per channel?
>>>>
>>>>Each channel has just two pins. Any channel can
>>>>
>>>>source 0-24 mA or 0-20 volts, CV/CC
>>>>
>>>>Regulate an external current loop, 0-32 mA
>>>>
>>>>Measure an external current loop, 0-32 mA
>>>>
>>>>Measure voltage (actually, it always measures current and voltage)
>>>>
>>>>Be an open.
>>>>
>>>>Be a short.
>>>
>>>Doesn't sound like a lot of data or computation. Wouldn't it have been
>>>simpler to isolate between the DAC and the CPU? That is, one processor?
>>
>> Each little CPU has a multiplexed ADC and a DAC in it, and the SPI
>> stuff, and a bunch of parallel ports. That's cheaper than putting a
>> separate ADC and DAC and ports up there. The CPU part is essentially
>> free. We use the individual, isolated CPUs to do the closed-loop
>> control, measurement, protections, and SPI up/down. The local control
>> loops will each run at 50 or 100K hits/second. If we did SPI up/down
>> to a single CPU, it couldn't run that fast, and the SPI traffic would
>> get huge if we tried.
>>
>> It is a little weird to think of getting a 100 MHz, 32-bit ARM CPU,
>> with RAM and flash, essentially for free when you buy the ADC and DAC.
>
>44MHz, aren't they? Or have you found a new one?

We're using the 80-pin LPC1758 in the channels. I think it runs at 100
MHz max.

================

The LPC1758/56/57/54/52/51 operate at CPU frequencies of up to 100
MHz. The LPC1759 operates at CPU frequencies of up to 120 MHz. The ARM
Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard
architecture with separate local instruction and data buses as well as
a third bus for peripherals. The ARM Cortex-M3 CPU also includes an
internal prefetch unit that supports speculative branching.

The peripheral complement of the LPC1759/58/56/54/52/51 includes up to
512 kB of flash memory, up to 64 kB of data memory, Ethernet MAC, USB
Device/Host/OTG interface, 8-channel general purpose DMA controller, 4
UARTs, 2 CAN channels, 2 SSP controllers, 2 2
SPI interface, 2 IC-bus interfaces, 2-input plus 2-output I S-bus
interface, 6 channel 12-bit ADC, 10-bit DAC, motor control PWM,
Quadrature Encoder interface, 4 general purpose timers, 6-output
general purpose PWM, ultra-low power Real-Time Clock (RTC)
with separate battery supply, and up to 52 general purpose I/O pins.

==============


That is truly insane for $6 or so. One of the NXP arms is under $1.

John

From: John Devereux on
John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> writes:

> On Fri, 11 Jun 2010 15:24:34 +0100, John Devereux
> <john(a)devereux.me.uk> wrote:
>
>>John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> writes:
>>
>>> On Thu, 10 Jun 2010 22:36:32 -0500, "krw(a)att.bizzzzzzzzzzzz"
>>> <krw(a)att.bizzzzzzzzzzzz> wrote:
>>>
>>>
>>>>>>>Here's the board.
>>>>>>>
>>>>>>>ftp://jjlarkin.lmi.net/V220.gif
>>>>>>>
>>>>>>>The 12 ARMs run down the middle. To their right are the data
>>>>>>>isolators, regulators, jtag connector, and dc/dc converter. The analog
>>>>>>>stuff is to the left.
>>>>>>>
>>>>>>>This is a 12-channel 4-20 mA sort of i/o board.
>>>>>>
>>>>>>How many I/O per channel?
>>>>>
>>>>>Each channel has just two pins. Any channel can
>>>>>
>>>>>source 0-24 mA or 0-20 volts, CV/CC
>>>>>
>>>>>Regulate an external current loop, 0-32 mA
>>>>>
>>>>>Measure an external current loop, 0-32 mA
>>>>>
>>>>>Measure voltage (actually, it always measures current and voltage)
>>>>>
>>>>>Be an open.
>>>>>
>>>>>Be a short.
>>>>
>>>>Doesn't sound like a lot of data or computation. Wouldn't it have been
>>>>simpler to isolate between the DAC and the CPU? That is, one processor?
>>>
>>> Each little CPU has a multiplexed ADC and a DAC in it, and the SPI
>>> stuff, and a bunch of parallel ports. That's cheaper than putting a
>>> separate ADC and DAC and ports up there. The CPU part is essentially
>>> free. We use the individual, isolated CPUs to do the closed-loop
>>> control, measurement, protections, and SPI up/down. The local control
>>> loops will each run at 50 or 100K hits/second. If we did SPI up/down
>>> to a single CPU, it couldn't run that fast, and the SPI traffic would
>>> get huge if we tried.
>>>
>>> It is a little weird to think of getting a 100 MHz, 32-bit ARM CPU,
>>> with RAM and flash, essentially for free when you buy the ADC and DAC.
>>
>>44MHz, aren't they? Or have you found a new one?
>
> We're using the 80-pin LPC1758 in the channels. I think it runs at 100
> MHz max.


>
>
> That is truly insane for $6 or so. One of the NXP arms is under $1.

Oh yes, nice looking chip, will be using it myself soon.

Sorry, I thought you were using ADUC7000 series for some reason. They do
match the description of a good ADC and DAC with a free ARM attached,
although not such a good one.

[...]

--

John Devereux
From: krw on
On Thu, 10 Jun 2010 21:21:53 -0700, John Larkin
<jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote:

>On Thu, 10 Jun 2010 22:36:32 -0500, "krw(a)att.bizzzzzzzzzzzz"
><krw(a)att.bizzzzzzzzzzzz> wrote:
>
>
>>>>>Here's the board.
>>>>>
>>>>>ftp://jjlarkin.lmi.net/V220.gif
>>>>>
>>>>>The 12 ARMs run down the middle. To their right are the data
>>>>>isolators, regulators, jtag connector, and dc/dc converter. The analog
>>>>>stuff is to the left.
>>>>>
>>>>>This is a 12-channel 4-20 mA sort of i/o board.
>>>>
>>>>How many I/O per channel?
>>>
>>>Each channel has just two pins. Any channel can
>>>
>>>source 0-24 mA or 0-20 volts, CV/CC
>>>
>>>Regulate an external current loop, 0-32 mA
>>>
>>>Measure an external current loop, 0-32 mA
>>>
>>>Measure voltage (actually, it always measures current and voltage)
>>>
>>>Be an open.
>>>
>>>Be a short.
>>
>>Doesn't sound like a lot of data or computation. Wouldn't it have been
>>simpler to isolate between the DAC and the CPU? That is, one processor?
>
>Each little CPU has a multiplexed ADC and a DAC in it, and the SPI
>stuff, and a bunch of parallel ports. That's cheaper than putting a
>separate ADC and DAC and ports up there. The CPU part is essentially
>free. We use the individual, isolated CPUs to do the closed-loop
>control, measurement, protections, and SPI up/down. The local control
>loops will each run at 50 or 100K hits/second. If we did SPI up/down
>to a single CPU, it couldn't run that fast, and the SPI traffic would
>get huge if we tried.
>
>It is a little weird to think of getting a 100 MHz, 32-bit ARM CPU,
>with RAM and flash, essentially for free when you buy the ADC and DAC.

Yes, I see your point. That is amazing.
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