Absolute value of a two's complement number
in [FPGA]
|
From: dlopez on 22 Apr 2010 18:54 >The absolute value of an n-bit signed value is at most an n-bit >unsigned value. (An n-bit unsigned value is an n+1 bit signed >value.) Does your absolute value need to be signed? > Ha this is what I was missing! Unsigned numbers still exist! Diego --------------------------------------- Posted through http://www.FPGARelated.com
From: glen herrmannsfeldt on 21 Apr 2010 23:28 dlopez <d(a)n_o_s_p_a_m.n_o_s_p_a_m.designgame.ca> wrote: > I'm trying to calculate the absolute value of a signed > number (two's complement). > Right now, I sign extend the input, and when msb=1, inverse all bits and > add 1. The sign extend is to take care of the most negative number. I suppose you can do that. I have never known anyone else to do that, but then on an N bit processor with N bit registers, it doesn't make much sense to try to store an N+1 bit value. > Is there a better way in terms of hardware utilization? > Here is my verilog code: > wire signed [w-1:0] a; > wire signed [w:0] b, c; > assign b = $signed(a); //sign exted input > assign c = b[w] ? (~b+1'b1) : b; //inverse all bits and add 1 if msb=1 -- glen
From: dlopez on 22 Apr 2010 00:35 >I suppose you can do that. I have never known anyone else >to do that, but then on an N bit processor with N bit registers, >it doesn't make much sense to try to store an N+1 bit value. So on a N bit processor with N bit registers, would you round that most negative value that doesn't fit to the max possible positive value? For example, say 4 bit data, -8 becomes 7? Diego --------------------------------------- Posted through http://www.FPGARelated.com
From: glen herrmannsfeldt on 22 Apr 2010 03:30 dlopez <d(a)n_o_s_p_a_m.n_o_s_p_a_m.designgame.ca> wrote: >>I suppose you can do that. I have never known anyone else >>to do that, but then on an N bit processor with N bit registers, >>it doesn't make much sense to try to store an N+1 bit value. > So on a N bit processor with N bit registers, would you round that most > negative value that doesn't fit to the max possible positive value? > For example, say 4 bit data, -8 becomes 7? On most processors, twos complement arithmetic wraps on overflow. In that case, absolute value of the most negative value gives the same, most negative, value. There are some with saturating arithmetic, such that give the largest value on overflow and smallest on underflow. In that case, I would expect the most positive value. Try it on your favorite processor and see what it does. -- glen
From: John_H on 22 Apr 2010 05:45 On Apr 21, 10:26 pm, "dlopez" <d(a)n_o_s_p_a_m.n_o_s_p_a_m.designgame.ca> wrote: > Hi, > I'm trying to calculate the absolute value of a signed number (two's > complement). > > Right now, I sign extend the input, and when msb=1, inverse all bits and > add 1. The sign extend is to take care of the most negative number. > > Is there a better way in terms of hardware utilization? > > Here is my verilog code: > > wire signed [w-1:0] a; > wire signed [w:0] b, c; > > assign b = $signed(a); //sign exted input > assign c = b[w] ? (~b+1'b1) : b; //inverse all bits and add 1 if msb=1 > > Thanks, > Diego > > --------------------------------------- > Posted throughhttp://www.FPGARelated.com The absolute value of an n-bit signed value is at most an n-bit unsigned value. (An n-bit unsigned value is an n+1 bit signed value.) Does your absolute value need to be signed? The ~b+1 seems like the best approach from a hardware standpoint. Looking at your technology view for whatever family you're using, you might see that you're better off doing the addition outside the conditional: assign c = (b[w] ? ~b : b) + {0,b[w]}; Given that signed math is one of the nastiest things in Verilog, I'm pretty certain the operations would be unsigned because the constant is unsigned but that shouldn't matter for absolute value.
|
Pages: 1 Prev: Problem with data2mem Next: Polmaddie Family CPLD and FPGA Teaching Boards |