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From: mpthompson on 10 Dec 2008 21:26
On a Xilinx Spartan 3e FPGA, I'm attempting to use the XPS MCH EMC
memory controller to connect with an 128Kx8 SRAM chip (CY62128DV30LL)
using Xilinx 10.1 EDK. If I attempt to specify the address bus as 17
bits in the MHS file I'll get the following error when generating the
bitstream:

-----------------------------------------------------------
ERROR:MDT - GLOBAL PORT:fpga_0_SRAM_A_pin CONNECTOR:fpga_0_SRAM_A -
C:\Xilinx\Projects\dlp-fpga_project_5\system.mhs line 21 - 32 bit-
width
connector assigned to 17 bit-width port
Completion time: 0.00 seconds
ERROR:MDT - platgen failed with errors!
-----------------------------------------------------------

If I specify the address bus width of the fpga_0_SRAM_A_pin vector to
be 32 bits the project will complete without errors. However, I then
have to specify IO definitions for address lines 17-31 in the UCF
file.

Is there some setting I can use in the MHS to get the Xilinx EDK to
accept that my address bus to the SRAM is 17 bits rather than 31
bits? I can't seem to find a parameter for the xps_mch_emc block that
lets me specify the width of the external address bus.

The relevant portions of the MHS file are show below.

Thanks!

Mike Thompson


-----------------------------------------------------------
....

PORT fpga_0_SRAM_DQ_pin = fpga_0_SRAM_DQ, DIR = IO, VEC = [7:0]
PORT fpga_0_SRAM_A_pin = fpga_0_SRAM_A, DIR = O, VEC = [16:0]
PORT fpga_0_SRAM_WEN_pin = fpga_0_SRAM_WEN, DIR = O
PORT fpga_0_SRAM_OEN_pin = fpga_0_SRAM_OEN, DIR = O, VEC = [0:0]
....

BEGIN xps_mch_emc
PARAMETER INSTANCE = SRAM
PARAMETER HW_VER = 2.00.a
PARAMETER C_MAX_MEM_WIDTH = 8
PARAMETER C_MEM0_WIDTH = 8
PARAMETER C_SYNCH_MEM_0 = 0
PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 20000
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
PARAMETER C_TCEDV_PS_MEM_0 = 70000
PARAMETER C_TWC_PS_MEM_0 = 50000
PARAMETER C_TAVDV_PS_MEM_0 = 70000
PARAMETER C_TWP_PS_MEM_0 = 50000
PARAMETER C_THZCE_PS_MEM_0 = 25000
PARAMETER C_TLZWE_PS_MEM_0 = 0
PARAMETER C_THZOE_PS_MEM_0 = 35000
PARAMETER C_XCL0_WRITEXFER = 0
PARAMETER C_MCH1_ACCESSBUF_DEPTH = 8
PARAMETER C_MEM0_BASEADDR = 0x81420000
PARAMETER C_MEM0_HIGHADDR = 0x8143ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE MCH0 = ixcl
BUS_INTERFACE MCH1 = dxcl
PORT Mem_A = fpga_0_SRAM_A
PORT Mem_DQ = fpga_0_SRAM_DQ
PORT Mem_WEN = fpga_0_SRAM_WEN
PORT Mem_OEN = fpga_0_SRAM_OEN
PORT RdClk = sys_clk_s
END
-----------------------------------------------------------

From: ales.gorkic on 11 Dec 2008 06:35
On Dec 11, 3:26 am, mpthompson <mpthomp...(a)gmail.com> wrote:
> On a Xilinx Spartan 3e FPGA, I'm attempting to use the XPS MCH EMC
> memory controller to connect with an 128Kx8 SRAM chip (CY62128DV30LL)
> using Xilinx 10.1 EDK. If I attempt to specify the address bus as 17
> bits in the MHS file I'll get the following error when generating the
> bitstream:
>
> -----------------------------------------------------------
> ERROR:MDT - GLOBAL PORT:fpga_0_SRAM_A_pin CONNECTOR:fpga_0_SRAM_A -
> C:\Xilinx\Projects\dlp-fpga_project_5\system.mhs line 21 - 32 bit-
> width
> connector assigned to 17 bit-width port
> Completion time: 0.00 seconds
> ERROR:MDT - platgen failed with errors!
> -----------------------------------------------------------
>
> If I specify the address bus width of the fpga_0_SRAM_A_pin vector to
> be 32 bits the project will complete without errors. However, I then
> have to specify IO definitions for address lines 17-31 in the UCF
> file.
>
> Is there some setting I can use in the MHS to get the Xilinx EDK to
> accept that my address bus to the SRAM is 17 bits rather than 31
> bits? I can't seem to find a parameter for the xps_mch_emc block that
> lets me specify the width of the external address bus.
>
> The relevant portions of the MHS file are show below.
>
> Thanks!
>
> Mike Thompson
>
> -----------------------------------------------------------
> ...
>
> PORT fpga_0_SRAM_DQ_pin = fpga_0_SRAM_DQ, DIR = IO, VEC = [7:0]
> PORT fpga_0_SRAM_A_pin = fpga_0_SRAM_A, DIR = O, VEC = [16:0]
> PORT fpga_0_SRAM_WEN_pin = fpga_0_SRAM_WEN, DIR = O
> PORT fpga_0_SRAM_OEN_pin = fpga_0_SRAM_OEN, DIR = O, VEC = [0:0]
> ...
>
> BEGIN xps_mch_emc
> PARAMETER INSTANCE = SRAM
> PARAMETER HW_VER = 2.00.a
> PARAMETER C_MAX_MEM_WIDTH = 8
> PARAMETER C_MEM0_WIDTH = 8
> PARAMETER C_SYNCH_MEM_0 = 0
> PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 20000
> PARAMETER C_NUM_BANKS_MEM = 1
> PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
> PARAMETER C_TCEDV_PS_MEM_0 = 70000
> PARAMETER C_TWC_PS_MEM_0 = 50000
> PARAMETER C_TAVDV_PS_MEM_0 = 70000
> PARAMETER C_TWP_PS_MEM_0 = 50000
> PARAMETER C_THZCE_PS_MEM_0 = 25000
> PARAMETER C_TLZWE_PS_MEM_0 = 0
> PARAMETER C_THZOE_PS_MEM_0 = 35000
> PARAMETER C_XCL0_WRITEXFER = 0
> PARAMETER C_MCH1_ACCESSBUF_DEPTH = 8
> PARAMETER C_MEM0_BASEADDR = 0x81420000
> PARAMETER C_MEM0_HIGHADDR = 0x8143ffff
> BUS_INTERFACE SPLB = mb_plb
> BUS_INTERFACE MCH0 = ixcl
> BUS_INTERFACE MCH1 = dxcl
> PORT Mem_A = fpga_0_SRAM_A
> PORT Mem_DQ = fpga_0_SRAM_DQ
> PORT Mem_WEN = fpga_0_SRAM_WEN
> PORT Mem_OEN = fpga_0_SRAM_OEN
> PORT RdClk = sys_clk_s
> END
> -----------------------------------------------------------

You are obviously trying to connect 17bit Address pins to 32bit port
defined in your xps_mch_emc. You shold properly adjust Address (A) bus
width in your peripheral. Take a look at S3E Starter Kit reference
design or build one with a BSB.

Cheers,

Ales
From: ales.gorkic on 11 Dec 2008 06:47
On Dec 11, 3:26 am, mpthompson <mpthomp...(a)gmail.com> wrote:
> On a Xilinx Spartan 3e FPGA, I'm attempting to use the XPS MCH EMC
> memory controller to connect with an 128Kx8 SRAM chip (CY62128DV30LL)
> using Xilinx 10.1 EDK. If I attempt to specify the address bus as 17
> bits in the MHS file I'll get the following error when generating the
> bitstream:
>
> -----------------------------------------------------------
> ERROR:MDT - GLOBAL PORT:fpga_0_SRAM_A_pin CONNECTOR:fpga_0_SRAM_A -
> C:\Xilinx\Projects\dlp-fpga_project_5\system.mhs line 21 - 32 bit-
> width
> connector assigned to 17 bit-width port
> Completion time: 0.00 seconds
> ERROR:MDT - platgen failed with errors!
> -----------------------------------------------------------
>
> If I specify the address bus width of the fpga_0_SRAM_A_pin vector to
> be 32 bits the project will complete without errors. However, I then
> have to specify IO definitions for address lines 17-31 in the UCF
> file.
>
> Is there some setting I can use in the MHS to get the Xilinx EDK to
> accept that my address bus to the SRAM is 17 bits rather than 31
> bits? I can't seem to find a parameter for the xps_mch_emc block that
> lets me specify the width of the external address bus.
>
> The relevant portions of the MHS file are show below.
>
> Thanks!
>
> Mike Thompson
>
> -----------------------------------------------------------
> ...
>
> PORT fpga_0_SRAM_DQ_pin = fpga_0_SRAM_DQ, DIR = IO, VEC = [7:0]
> PORT fpga_0_SRAM_A_pin = fpga_0_SRAM_A, DIR = O, VEC = [16:0]
> PORT fpga_0_SRAM_WEN_pin = fpga_0_SRAM_WEN, DIR = O
> PORT fpga_0_SRAM_OEN_pin = fpga_0_SRAM_OEN, DIR = O, VEC = [0:0]
> ...
>
> BEGIN xps_mch_emc
> PARAMETER INSTANCE = SRAM
> PARAMETER HW_VER = 2.00.a
> PARAMETER C_MAX_MEM_WIDTH = 8
> PARAMETER C_MEM0_WIDTH = 8
> PARAMETER C_SYNCH_MEM_0 = 0
> PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 20000
> PARAMETER C_NUM_BANKS_MEM = 1
> PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
> PARAMETER C_TCEDV_PS_MEM_0 = 70000
> PARAMETER C_TWC_PS_MEM_0 = 50000
> PARAMETER C_TAVDV_PS_MEM_0 = 70000
> PARAMETER C_TWP_PS_MEM_0 = 50000
> PARAMETER C_THZCE_PS_MEM_0 = 25000
> PARAMETER C_TLZWE_PS_MEM_0 = 0
> PARAMETER C_THZOE_PS_MEM_0 = 35000
> PARAMETER C_XCL0_WRITEXFER = 0
> PARAMETER C_MCH1_ACCESSBUF_DEPTH = 8
> PARAMETER C_MEM0_BASEADDR = 0x81420000
> PARAMETER C_MEM0_HIGHADDR = 0x8143ffff
> BUS_INTERFACE SPLB = mb_plb
> BUS_INTERFACE MCH0 = ixcl
> BUS_INTERFACE MCH1 = dxcl
> PORT Mem_A = fpga_0_SRAM_A
> PORT Mem_DQ = fpga_0_SRAM_DQ
> PORT Mem_WEN = fpga_0_SRAM_WEN
> PORT Mem_OEN = fpga_0_SRAM_OEN
> PORT RdClk = sys_clk_s
> END
> -----------------------------------------------------------

One more thing. Usually the bus is splitted with "util_bus_split" core.
From: Brian Drummond on 11 Dec 2008 08:12
On Wed, 10 Dec 2008 18:26:37 -0800 (PST), mpthompson
<mpthompson(a)gmail.com> wrote:

>On a Xilinx Spartan 3e FPGA, I'm attempting to use the XPS MCH EMC
>memory controller to connect with an 128Kx8 SRAM chip (CY62128DV30LL)
>using Xilinx 10.1 EDK.
>
>If I specify the address bus width of the fpga_0_SRAM_A_pin vector to
>be 32 bits the project will complete without errors. However, I then
>have to specify IO definitions for address lines 17-31 in the UCF
>file.

In EDK 7.1 there used to be an IP core you could instantiate, simply to
extract a slice out of a longer word. Maybe it's still there? (Sorry, I
can't remember its name but it should be easy to find)

It seemed like a sledgehammer to crack a nut, but it kept the design
within the EDK [paradigm|straitjacket], and I think it will do what you
want.

Instead I just used my EDK project as a component within an ISE project,
so I was free to do anything I wanted outside it.

- Brian

From: Bryan on 11 Dec 2008 12:46
Avnet has an example using a 1Mx8 Cypress MicroPower SRAM with
Spartan-3A MicroBlaze (EDK 10.1.3). You can find it at www.em.avnet.com/mxp-sram
--> Support Files & Downloads. The example was generated using BSB,
which automatically instantiates IP UTIL_BUS_SPLIT to align the
busses.

Bryan

PORT fpga_0_SRAM_1Mx8_Mem_A_pin = fpga_0_SRAM_1Mx8_Mem_A, DIR = O,
VEC = [12:31]
PORT fpga_0_SRAM_1Mx8_Mem_DQ_pin = fpga_0_SRAM_1Mx8_Mem_DQ, DIR = IO,
VEC = [0:7]
PORT fpga_0_SRAM_1Mx8_Mem_OEN_pin = fpga_0_SRAM_1Mx8_Mem_OEN, DIR =
O, VEC = [0:0]
PORT fpga_0_SRAM_1Mx8_Mem_CEN_pin = fpga_0_SRAM_1Mx8_Mem_CEN, DIR =
O, VEC = [0:0]
PORT fpga_0_SRAM_1Mx8_Mem_WEN_pin = fpga_0_SRAM_1Mx8_Mem_WEN, DIR = O
PORT fpga_0_SRAM_1Mx8_Mem_CE_pin = fpga_0_SRAM_1Mx8_Mem_CE, DIR = O,
VEC = [0:0]

BEGIN xps_mch_emc
PARAMETER INSTANCE = SRAM_1Mx8
PARAMETER HW_VER = 2.00.a
PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 20833
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
PARAMETER C_SYNCH_MEM_0 = 0
PARAMETER C_MEM0_WIDTH = 8
PARAMETER C_MAX_MEM_WIDTH = 8
PARAMETER C_TCEDV_PS_MEM_0 = 45000
PARAMETER C_TWC_PS_MEM_0 = 35000
PARAMETER C_TAVDV_PS_MEM_0 = 45000
PARAMETER C_TWP_PS_MEM_0 = 35000
PARAMETER C_THZCE_PS_MEM_0 = 0
PARAMETER C_TLZWE_PS_MEM_0 = 0
PARAMETER C_MCH0_ACCESSBUF_DEPTH = 4
PARAMETER C_XCL0_WRITEXFER = 0
PARAMETER C_MCH1_ACCESSBUF_DEPTH = 8
PARAMETER C_MEM0_BASEADDR = 0x84900000
PARAMETER C_MEM0_HIGHADDR = 0x849fffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE MCH0 = ixcl
BUS_INTERFACE MCH1 = dxcl
PORT Mem_A = fpga_0_SRAM_1Mx8_Mem_A_split
PORT Mem_DQ = fpga_0_SRAM_1Mx8_Mem_DQ
PORT Mem_OEN = fpga_0_SRAM_1Mx8_Mem_OEN
PORT Mem_CEN = fpga_0_SRAM_1Mx8_Mem_CEN
PORT Mem_WEN = fpga_0_SRAM_1Mx8_Mem_WEN
PORT Mem_CE = fpga_0_SRAM_1Mx8_Mem_CE
PORT RdClk = sys_clk_s
END

BEGIN util_bus_split
PARAMETER INSTANCE = SRAM_1Mx8_util_bus_split_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE_IN = 32
PARAMETER C_LEFT_POS = 0
PARAMETER C_SPLIT = 12
PORT Sig = fpga_0_SRAM_1Mx8_Mem_A_split
PORT Out2 = fpga_0_SRAM_1Mx8_Mem_A
END


On Dec 11, 6:12 am, Brian Drummond <brian_drumm...(a)btconnect.com>
wrote:
> On Wed, 10 Dec 2008 18:26:37 -0800 (PST), mpthompson
>
> <mpthomp...(a)gmail.com> wrote:
> >On a Xilinx Spartan 3e FPGA, I'm attempting to use the XPS MCH EMC
> >memory controller to connect with an 128Kx8 SRAM chip (CY62128DV30LL)
> >using Xilinx 10.1 EDK.  
>
> >If I specify the address bus width of the fpga_0_SRAM_A_pin vector to
> >be 32 bits the project will complete without errors.  However, I then
> >have to specify IO definitions for address lines 17-31 in the UCF
> >file.
>
> In EDK 7.1 there used to be an IP core you could instantiate, simply to
> extract a slice out of a longer word. Maybe it's still there? (Sorry, I
> can't remember its name but it should be easy to find)
>
> It seemed like a sledgehammer to crack a nut, but it kept the design
> within the EDK [paradigm|straitjacket], and I think it will do what you
> want.
>
> Instead I just used my EDK project as a component within an ISE project,
> so I was free to do anything I wanted outside it.
>
> - Brian

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