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From: Rob on 24 Jul 2010 21:15
Hi,

Using Altera Model-Sim to do a gate level simulation. The .vo file that
is produced doesn't seem to be modeling the internal RAM's correctly. In
the design they are instantiated as 12bit but the EDA netlist has them
as 4 bits.

Any help on this? Has anyone experienced a similar problem?

Regards,
Rob
From: KJ on 24 Jul 2010 22:33
On Jul 24, 9:15 pm, Rob <noth...(a)nowhere.com> wrote:
> Hi,
>
> Using Altera Model-Sim to do a gate level simulation. The .vo file that
> is produced doesn't seem to be modeling the internal RAM's correctly. In
> the design they are instantiated as 12bit but the EDA netlist has them
> as 4 bits.
>

Answer these questions first:
1. Does the gate level simulation *results* not match the original sim
*results*?
2. Are you questioning the validity of the .vo file based solely on a
visual inspection of the .vo file?

If you can only answer 'yes' to question #2, then go back to determine
the answer to question #1 first. Since you say "doesn't seem to..."
I'm guessing that question #1 hasn't been answered yet.

> Any help on this? Has anyone experienced a similar problem?
>
I have had other cases where post-route sim was not correct because of
incorrect synthesis from Quartus...not often, but at least two cases
that I recall off the top of my head.

If your answer to question #1 is that the post-route sim is not
correct, then the method to fix it is...
1. Create a testbench with pre- and post-route simulation models both
instantiated. Demonstrate that incorrect results are being generated.
2. Write up a description of how to run the sim and how the post-route
sim differs
3. Submit your write up as a case to Altera
4. Start working on a hypothesis for what might be wrong and start
developing some way to work around the bug.

Steps 1 thru 3 help Altera improve Quartus which long term helps you
and others. Step 4 helps you get your current design working.

If instead your answer to question #2 is that the post-route sim is
correct, then here are some possibilities:
- Your testbench does not adequately exercise the memory in such a way
that it results in any difference to any I/O pin. If so, then beef up
the testbench to that level.
- 8 of the output data bits from the memory are either not used, or
connected to logic which ultimately does not connect to any output pin
of the device. In short, those 8 bits were reduced out and not
needed.
- You're misinterpreting the .vo file in some fashion. Maybe there
are three 4 bit memories instantiated in the actual implementation.

Kevin Jennings
From: Rob on 24 Jul 2010 23:43
I mis-read the .vo file. It is implementing the 12 bit ram as three
4-bit memories.

Rob wrote:
> Hi,
>
> Using Altera Model-Sim to do a gate level simulation. The .vo file that
> is produced doesn't seem to be modeling the internal RAM's correctly. In
> the design they are instantiated as 12bit but the EDA netlist has them
> as 4 bits.
>
> Any help on this? Has anyone experienced a similar problem?
>
> Regards,
> Rob
From: Rob on 24 Jul 2010 23:45
I read this post, just as I was coming back to the group to update my
findings, which were as you also mention below. The 12 bit memory is
instantiated as three 4-bit memories.

Thanks,
Rob

KJ wrote:
> On Jul 24, 9:15 pm, Rob <noth...(a)nowhere.com> wrote:
>> Hi,
>>
>> Using Altera Model-Sim to do a gate level simulation. The .vo file that
>> is produced doesn't seem to be modeling the internal RAM's correctly. In
>> the design they are instantiated as 12bit but the EDA netlist has them
>> as 4 bits.
>>
>
> Answer these questions first:
> 1. Does the gate level simulation *results* not match the original sim
> *results*?
> 2. Are you questioning the validity of the .vo file based solely on a
> visual inspection of the .vo file?
>
> If you can only answer 'yes' to question #2, then go back to determine
> the answer to question #1 first. Since you say "doesn't seem to..."
> I'm guessing that question #1 hasn't been answered yet.
>
>> Any help on this? Has anyone experienced a similar problem?
>>
> I have had other cases where post-route sim was not correct because of
> incorrect synthesis from Quartus...not often, but at least two cases
> that I recall off the top of my head.
>
> If your answer to question #1 is that the post-route sim is not
> correct, then the method to fix it is...
> 1. Create a testbench with pre- and post-route simulation models both
> instantiated. Demonstrate that incorrect results are being generated.
> 2. Write up a description of how to run the sim and how the post-route
> sim differs
> 3. Submit your write up as a case to Altera
> 4. Start working on a hypothesis for what might be wrong and start
> developing some way to work around the bug.
>
> Steps 1 thru 3 help Altera improve Quartus which long term helps you
> and others. Step 4 helps you get your current design working.
>
> If instead your answer to question #2 is that the post-route sim is
> correct, then here are some possibilities:
> - Your testbench does not adequately exercise the memory in such a way
> that it results in any difference to any I/O pin. If so, then beef up
> the testbench to that level.
> - 8 of the output data bits from the memory are either not used, or
> connected to logic which ultimately does not connect to any output pin
> of the device. In short, those 8 bits were reduced out and not
> needed.
> - You're misinterpreting the .vo file in some fashion. Maybe there
> are three 4 bit memories instantiated in the actual implementation.
>
> Kevin Jennings
From: dgreig on 26 Jul 2010 03:54
On Jul 25, 2:15 am, Rob <noth...(a)nowhere.com> wrote:
> Hi,
>
> Using Altera Model-Sim to do a gate level simulation. The .vo file that
> is produced doesn't seem to be modeling the internal RAM's correctly. In
> the design they are instantiated as 12bit but the EDA netlist has them
> as 4 bits.
>
> Any help on this? Has anyone experienced a similar problem?
>
> Regards,
> Rob

Best to read the memory section of the device datasheet to see why
it's splitting into 3 x 4 bit blocks. For example a M9k in stratix can
be split into following during synthesis:
8K×1
4K×2
2K×4
1K×8
1K×9
512×16
512×18
256×32
256×36
What your seeing is expected behaviour.

Best Regards
DG
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