Prev: Prog4 - Altera Programming Cable and a development board in one.
Next: Power Management for PCIe
From: Nial Stewart on 14 Jun 2010 09:04
> > Altera devices can't implement LUT based distributed memory, this is one of
> > Xilinx's heavily patented uniqe selling points!

> If it's so heavily patented, why do Lattice devices support
> distributed RAM? There must be some work-arounds to the
> existing patents.

Licensing?

It's a useful feature so I presumed (and have read here I think) the thing
stopping the other vendors implementing it is patents.


Nial.



From: General Schvantzkoph on 14 Jun 2010 10:12
On Mon, 14 Jun 2010 13:06:44 +0100, Nial Stewart wrote:

> "newzhnd" <nobody(a)home.com> wrote in message
> news:XaeRn.26714$%u7.16071(a)newsfe14.iad...
>> Help !!! The megawizard in Quartus 2 does not seem to support
>> generating small roms & rams using the LUT
>> tables, only using the M9K memory blocks. Any way to generate small
>> roms & rams using the logic cells ?
>> I'm looking for something similar to Xilinx distributed memory
>> generator.
>
>
> Altera devices can't implement LUT based distributed memory, this is one
> of Xilinx's heavily patented uniqe selling points!
>
> You just have to use device logic or M9Ks.
>
>
> Nial.

They can implement ROMs with LUTs, all logic in a LUT based FPGA is a
ROM. The LUT RAM patent was filed in 1989 and granted in 1994 so it
should expire next year, the patent term was 17 years from the date of
grant in the early 90s.
From: Antti on 14 Jun 2010 12:59
On Jun 14, 3:25 pm, Gabor <ga...(a)alacron.com> wrote:
> On Jun 14, 8:06 am, "Nial Stewart"
>
> <nial*REMOVE_TH...(a)nialstewartdevelopments.co.uk> wrote:
> > "newzhnd" <nob...(a)home.com> wrote in messagenews:XaeRn.26714$%u7.16071(a)newsfe14.iad...
> > > Help !!!   The megawizard in Quartus 2 does not seem to support generating small roms & rams using
> > > the LUT
> > > tables, only using the M9K memory blocks.  Any way to generate small roms & rams using the logic
> > > cells ?
> > > I'm looking for something similar to Xilinx distributed memory generator.
>
> > Altera devices can't implement LUT based distributed memory, this is one of
> > Xilinx's heavily patented uniqe selling points!
>
> > You just have to use device logic or M9Ks.
>
> > Nial.
>
> If it's so heavily patented, why do Lattice devices support
> distributed RAM?  There must be some work-arounds to the
> existing patents.

very simple: Lattice has the license!
because AT&T used to to manufacture Xilinx compatible FPGA's
and Lattice is the current license holder of those old technologies
hence Lattice inherited the rights to use LUT as distributed RAM.

Other FPGA vendors like Altera can not do it without legal issues

Antti








From: Phil Jessop on 14 Jun 2010 13:36

"newzhnd" <nobody(a)home.com> wrote in message
news:JxeRn.38054$rU6.33631(a)newsfe10.iad...
> I'd rather not write verilog & specify each rom or ram word individually.
> Cyclone 2 supports logic cell usage
> for rom or ram. I'm surprised cyclone 3 doesn't. Xilinx allows either LUT
> or block memory for ram or rom.
> Nothing to do with sync or async.
>
> "glen herrmannsfeldt" <gah(a)ugcs.caltech.edu> wrote in message
> news:hv3rmb$ul3$1(a)speranza.aioe.org...
>> newzhnd <nobody(a)home.com> wrote:
>>
>>> Help !!! The megawizard in Quartus 2 does not seem to support
>>> generating
>>> small roms & rams using the LUT
>>> tables, only using the M9K memory blocks. Any way to generate small
>>> roms &
>>> rams using the logic cells ?
>>> I'm looking for something similar to Xilinx distributed memory
>>> generator.
>>> TIA.
>>
>> Can't you just generate them in ordinary verilog or VHDL?
>>
>> For Xilinx, the RAM arrays are synchronous, so it has to generate
>> LUT RAM (or ROM) if it is used asynchronously.
>>
>> -- glen
>
>


Just use the LPM_CONSTANT primitive and specify the bit width and value. I
am sure you can take it from there ....


From: Michael S on 14 Jun 2010 19:33
On Jun 14, 2:06 pm, "Nial Stewart"
<nial*REMOVE_TH...(a)nialstewartdevelopments.co.uk> wrote:
> "newzhnd" <nob...(a)home.com> wrote in messagenews:XaeRn.26714$%u7.16071(a)newsfe14.iad...
> > Help !!!   The megawizard in Quartus 2 does not seem to support generating small roms & rams using
> > the LUT
> > tables, only using the M9K memory blocks.  Any way to generate small roms & rams using the logic
> > cells ?
> > I'm looking for something similar to Xilinx distributed memory generator.
>
> Altera devices can't implement LUT based distributed memory, this is one of
> Xilinx's heavily patented uniqe selling points!
>

In fact Stratix3/4 and Aria2 support MLAB which is very similar to
Xilinx distributed memory. So obviously they found a hole in Xilinx
patent.

> You just have to use device logic or M9Ks.

For RAM on C2 - yes. Except, it's M4K rather than M9K
As already mentioned here, even on C2 synthesis tools should be able
to implement small ROM in LUTs.
However, AFAIR, Quartus-II does not support initializing of such ROM
from .mif or .hex file so every change of the ROM contest would
require full recompilation.

>
> Nial.

First  |  Prev  | 
Pages: 1 2
Prev: Prog4 - Altera Programming Cable and a development board in one.
Next: Power Management for PCIe