Prev: Ethernet development kit
Next: Actel is now the only FPGA vendor with hard-core processor in the latest family
From: emeb on 4 Mar 2010 11:32
On Mar 4, 5:31 am, "Nial Stewart"
<nial*REMOVE_TH...(a)nialstewartdevelopments.co.uk> wrote:
> >www.1pin-interface.com
>
> I've been emailed to say that some people are having problems with this.
>
> This is based on a Tiddlywiki, a quick google shows that the Skype plug-in
> breaks some wiki-sites. It's in the Skype bug list to be fixed.
>
> If you do have any problems try disabling Skype to view it.
>
> Hardly an auspicious start. :-(
>
> Nial

Looks interesting. A few administrative observations:

* I get '404' pages for the target VHDL and Schematics on the Download
pages.
* the links in your prior messages are missing the 'http://' so they
need to be cut/pasted into the browser rather than just clicking to
follow.

Conceptually attractive - I like the idea of an inexpensive USB
interface for internal access to FPGAs. Something along the lines of
Chipscope. I don't much care for the need to use Excel as the front-
end. For those of us who don't use Excel or have access to VBA is
there any possibility of a document that describes the protocol so
that other languages & apps can be used to access it, or is that level
of detail proprietary?

Eric
From: Nial Stewart on 4 Mar 2010 12:06
> Looks interesting. A few administrative observations:
> * I get '404' pages for the target VHDL and Schematics on the Download
> pages.

This should be mostly fixed, I don't seem to be able to link to a *.vhd
file for some reason but have changed it to *.txt. Just change the file
ending and it should work.

I'll try it fix it properly later.

> * the links in your prior messages are missing the 'http://' so they
> need to be cut/pasted into the browser rather than just clicking to
> follow.

It looks like this is a Google problem, other newsreaders pick up the
URLs properly, but thanks again.

> Conceptually attractive - I like the idea of an inexpensive USB
> interface for internal access to FPGAs. Something along the lines of
> Chipscope.

Yes, but at a slightly higher functional level.

Chipscope/Signal Tap are for monitoring individual lines/groups (AFAIK).

The 1 Pin Interface is more targeted towards reading or driving
status or control registers.

The idea is to have a convenient/compact interface that replaces
an RS232 type debug interface and removes the need for external
power supplies for level convertors etc. And only uses one pin.

> I don't much care for the need to use Excel as the front-
> end.

I started using C++ builder but switched to Excel because it's
almost universal. BTW, if you have access to Excel the VBA editor
is integrated, just hit Alt-F11.

It's obviously not universal enough!

> For those of us who don't use Excel or have access to VBA is
> there any possibility of a document that describes the protocol so
> that other languages & apps can be used to access it, or is that level
> of detail proprietary?

Yes no problem, I want to to be as open as possible, as long as you
don't expect support for strange languages. I'll probably publish the
code for the 1 pin module if there's any demand.

I'll add a page to the Web site lising the text of the Excel module
tonight. This is probably the simplest way of explaining what's happening.


Thanks for the feedback.

Nial






From: emeb on 4 Mar 2010 13:44
On Mar 4, 10:06 am, "Nial Stewart"
<nial*REMOVE_TH...(a)nialstewartdevelopments.co.uk> wrote:
> > Looks interesting. A few administrative observations:
> > * I get '404' pages for the target VHDL and Schematics on the Download
> > pages.
>
> This should be mostly fixed, I don't seem to be able to link to a *.vhd
> file for some reason but have changed it to *.txt. Just change the file
> ending and it should work.

Yep - I'm now able to get both of those items.

> > Conceptually attractive - I like the idea of an inexpensive USB
> > interface for internal access to FPGAs. Something along the lines of
> > Chipscope.
>
> Yes, but at a slightly higher functional level.
>
> Chipscope/Signal Tap are for monitoring individual lines/groups (AFAIK).

Yes, now that I've seen the way the target works it appears to be a 4k
bank of 16-bit read/write registers. Chipscope gives a more fine-
grained access than that, although one can build similar structures in
the GUI. Any other debugging function (bit access, logic analyzers,
etc) could be easily layered on top of the register structure so it's
functionally complete.

As I've mentioned elsewhere, one of my gripes with Chipscope is that
all access to the Virtual I/O and Internal Logic Analyzers is mediated
by their WinXX GUI app, and that can't be scripted or controlled by
anything except user mouse clicks. They have a rudimentary TCL
interface, but it doesn't know how to access the VIOs and ILAs - it
just gives access to the JTAG TAP controller. Having algorithmic
access to the FPGA guts would be a big help, and right now I have to
do that via other means (extra logic on the board that's controlled by
the PC, etc).

> > there any possibility of a document that describes the protocol so
> > that other languages & apps can be used to access it, or is that level
> > of detail proprietary?
>
> Yes no problem, I want to to be as open as possible, as long as you
> don't expect support for strange languages. I'll probably publish the
> code for the 1 pin module if there's any demand.
>
> I'll add a page to the Web site lising the text of the Excel module
> tonight. This is probably the simplest way of explaining what's happening..

Sounds good. Thanks for making this available.

Eric
From: -jg on 4 Mar 2010 14:01
On Mar 5, 6:06 am, "Nial Stewart"
<nial*REMOVE_TH...(a)nialstewartdevelopments.co.uk> wrote:
> > I don't much care for the need to use Excel as the front-
> > end.
>
> I started using C++ builder but switched to Excel because it's
> almost universal. BTW, if you have access to Excel the VBA editor
> is integrated, just hit Alt-F11.
>
> It's obviously not universal enough!

So, does it work with OpenOffice ?


> Yes no problem, I want to to be as open as possible, as long as you
> don't expect support for strange languages. I'll probably publish the
> code for the 1 pin module if there's any demand.

I could not see an example timing/protocol diagram ?

The other uses that spring to mind are

* Use with a Microcontroller, in which case a SW-pin version on the
target would be needed.
Might be as simple as a slow enough clock ?

* Use with CPLDs, in this case, minimal-logic is the requirement.

-jg
From: Nial Stewart on 4 Mar 2010 16:15
> > Yes, but at a slightly higher functional level.
> > Chipscope/Signal Tap are for monitoring individual lines/groups (AFAIK).

> Yes, now that I've seen the way the target works it appears to be a 4k
> bank of 16-bit read/write registers.

Yes, but you only need to implement the address span and data depth in
the Target FPGA that's required.

I've often used it with fewer than 8 target registers.

Your synthesis tool should then optimise out any logic that isn't
required.

> > I'll add a page to the Web site lising the text of the Excel module
> > tonight. This is probably the simplest way of explaining what's happening.

> Sounds good. Thanks for making this available.


OK, it's not a seperate page but I've added the VBA OnePinModule as
a text file in Downloads with a note in Host Software.

Please no sniggering about my software 'prowess', it took me a while to
get it all going.


Nial



 |  Next  |  Last
Pages: 1 2 3
Prev: Ethernet development kit
Next: Actel is now the only FPGA vendor with hard-core processor in the latest family