Prev: Xilinx' partition flow in ISE12.1
Next: How to create a LVPECL_25 output pair (Spartan3, ISE 9.1)
From: Markus Lavin on 21 Jul 2010 03:27 Hi all, This is a post to announce the existence of the AjarDSP project, an attempt to design and implement an open source VLIW DSP with an open source tool chain (assembler, simulator/debugger and C compiler). Check out the details at: http://code.google.com/p/ajardsp/ regards Markus
From: Jason on 21 Jul 2010 10:26 On Jul 21, 3:27 am, Markus Lavin <markusl.se78pleasenos...(a)gmail.com> wrote: > Hi all, > > This is a post to announce the existence of the AjarDSP project, an > attempt to design and implement an open source VLIW DSP with an open > source tool chain (assembler, simulator/debugger and C compiler). > > Check out the details at:http://code.google.com/p/ajardsp/ > > regards > Markus Looks like a pretty ambitious project; good luck. It looks to me that your design was heavily influenced by TI's C55x family? It does appear to have a number of enhancements above any of those devices though (more registers, more parallelism). Jason
From: Markus Lavin on 22 Jul 2010 02:31 On 21 Juli, 16:26, Jason <cincy...(a)gmail.com> wrote: > On Jul 21, 3:27 am, Markus Lavin <markusl.se78pleasenos...(a)gmail.com> > wrote: > > > Hi all, > > > This is a post to announce the existence of the AjarDSP project, an > > attempt to design and implement an open source VLIW DSP with an open > > source tool chain (assembler, simulator/debugger and C compiler). > > > Check out the details at:http://code.google.com/p/ajardsp/ > > > regards > > Markus > > Looks like a pretty ambitious project; good luck. Thanks! > It looks to me that > your design was heavily influenced by TI's C55x family? That is possible, but not really intentional. I would say that given that certain design parameters are fixed (like 16-bit dual-mac, 64-bit VLIW bundles, etc) then once you start to consider instruction encoding you aren't left with that much freedom. At least not if one wants to go for the more obvious solutions. > It does appear > to have a number of enhancements above any of those devices though > (more registers, more parallelism). > > Jason Markus
From: Andreas Ehliar on 27 Jul 2010 17:21 On 2010-07-21, Markus Lavin <markusl.se78pleasenospam(a)gmail.com> wrote: > Hi all, > > This is a post to announce the existence of the AjarDSP project, an > attempt to design and implement an open source VLIW DSP with an open > source tool chain (assembler, simulator/debugger and C compiler). > > Check out the details at: http://code.google.com/p/ajardsp/ This sounds very interesting. I have contemplated doing something similar a long time as there were no FPGA optimized DSP processor available that I'm was aware of, but in the end I got stuck creating a fairly general purpose FPGA optimized processor instead. Are you doing this just for fun or do you have some specific applications in mind? /Andreas
From: Markus Lavin on 28 Jul 2010 08:40 On 27 Juli, 20:21, Andreas Ehliar <ehliar-nos...(a)isy.liu.se> wrote: > On 2010-07-21, Markus Lavin <markusl.se78pleasenos...(a)gmail.com> wrote: > > > Hi all, > > > This is a post to announce the existence of theAjarDSPproject, an > > attempt to design and implement an open source VLIW DSP with an open > > source tool chain (assembler, simulator/debugger and C compiler). > > > Check out the details at:http://code.google.com/p/ajardsp/ > > This sounds very interesting. I have contemplated doing something similar > a long time as there were no FPGA optimized DSP processor available that > I'm was aware of, but in the end I got stuck creating a fairly general > purpose FPGA optimized processor instead. I agree, this is a very interesting subject and there does indeed seem to be a lack of open source DSP implementations available on the net. However, at this point in time I would not consider AjarDSP to be in any way FPGA optimized. It is approaching a feature complete phase and after that focus will naturally shift to trying to increase speed and reduce area. Somewhere inbetween it would also be interesting to evaluate the 'compiler friendliness' of certain architectural features... > > Are you doing this just for fun or do you have some specific applications > in mind? No, there is no specific application in mind except perhaps some demo in the area of audio processing. The goal for the project is simply to provide the DSP and the tools. In the end hopefully someone will find it useful and maybe consider it for use in some product. In the meantime I consider this CV improvement and of course I can't deny that it is quite fun to work on every now and then :) /Markus
|
Next
|
Last
Pages: 1 2 Prev: Xilinx' partition flow in ISE12.1 Next: How to create a LVPECL_25 output pair (Spartan3, ISE 9.1) |