Asynchronous FIFO and almost empty - bug?
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From: heinerlitz on 29 Nov 2007 06:46 Hi, we are using an asynchronous FIFO to bridge two clock domains. Both domains have "the same" clock speed but different clock oscillators. We shift data phits in the FIFO which always form a data packet. In between a packet data is shifted in continously without a break. Breaks (no shift in) are only allowed in between packets. On the output side of the FIFO we need a steady data stream during a data packet. The packet may not be interrupted. As the input side may be slower we start shift-out data if at least two data phits are in the FIFO. As the 2 clocks have almost the same frequency this guarantees that we never have a buffer underflow. The problem we found is that the almost empty flag is only asserted if the FIFO is beeing emptied and not if it is beeing filled. So if the FIFO was empty and we get a shift in the almost empty is not asserted although we set the treshold to one. Is this a bug? We tried to solve that problem by generating a delay-empty signal at the output which guarantees that if the FIFO was emtpy and than receives a shift in we still wait another cycle so we get another shift in to avoid underflow. This solution however does not solve the problem if the FIFO exactly had one entry when starting to shift out a packet. In this case neither delayed-empty nor almost empty is asserted, hence we get an underflow. Why isn't the almost empty signal asserted every time there is a single packet in the FIFO? Ideas?
From: Peter Alfke on 29 Nov 2007 11:35 On Nov 29, 3:46 am, "heinerl...(a)googlemail.com" <heinerl...(a)googlemail.com> wrote: > Hi, > > we are using an asynchronous FIFO to bridge two clock domains. Both > domains have "the same" clock speed but different clock oscillators. > > We shift data phits in the FIFO which always form a data packet. In > between a packet data is shifted in continously without a break. > Breaks (no shift in) are only allowed in between packets. > On the output side of the FIFO we need a steady data stream during a > data packet. The packet may not be interrupted. As the input side may > be slower we start shift-out data if at least two data phits are in > the FIFO. As the 2 clocks have almost the same frequency this > guarantees that we never have a buffer underflow. > > The problem we found is that the almost empty flag is only asserted if > the FIFO is beeing emptied and not if it is beeing filled. So if the > FIFO was empty and we get a shift in the almost empty is not asserted > although we set the treshold to one. Is this a bug? Which FPGA family, which type of FIFO controller, and also what clock rate? Peter Alfke, Xilinx Applications> > We tried to solve that problem by generating a delay-empty signal at > the output which guarantees that if the FIFO was emtpy and than > receives a shift in we still wait another cycle so we get another > shift in to avoid underflow. > > This solution however does not solve the problem if the FIFO exactly > had one entry when starting to shift out a packet. In this case > neither delayed-empty nor almost empty is asserted, hence we get an > underflow. > > Why isn't the almost empty signal asserted every time there is a > single packet in the FIFO? Ideas?
From: Peter Alfke on 29 Nov 2007 12:26 On Nov 29, 3:46 am, "heinerl...(a)googlemail.com" <heinerl...(a)googlemail.com> wrote: > Hi, > > we are using an asynchronous FIFO to bridge two clock domains. Both > domains have "the same" clock speed but different clock oscillators. > > We shift data phits in the FIFO which always form a data packet. In > between a packet data is shifted in continously without a break. > Breaks (no shift in) are only allowed in between packets. > On the output side of the FIFO we need a steady data stream during a > data packet. The packet may not be interrupted. As the input side may > be slower we start shift-out data if at least two data phits are in > the FIFO. As the 2 clocks have almost the same frequency this > guarantees that we never have a buffer underflow. > > The problem we found is that the almost empty flag is only asserted if > the FIFO is beeing emptied and not if it is beeing filled. So if the > FIFO was empty and we get a shift in the almost empty is not asserted > although we set the treshold to one. Is this a bug? In a synchronous (single-clock) FIFO, flag control is very simple, done by a synchronous state machine. With asynchronous (unrelated clocks) operation, flag control is very complex, if metastable posssibilities must also be considered. Almost Empty is generally considered a warning flag that can have a one-count ambiguity. Empty is the most important flag, and its rising edge is not allowed to have any uncertainty. The trailing edge of EMPTY, however, often has an additional delay, so as to avoid metastability. My advice: trust the rising edge of the Empty flag, expect its falling edge to have an additional pipeline delay, and treat the Almost Empty flag just as a warning. Peter Alfke > We tried to solve that problem by generating a delay-empty signal at > the output which guarantees that if the FIFO was emtpy and than > receives a shift in we still wait another cycle so we get another > shift in to avoid underflow. > > This solution however does not solve the problem if the FIFO exactly > had one entry when starting to shift out a packet. In this case > neither delayed-empty nor almost empty is asserted, hence we get an > underflow. > > Why isn't the almost empty signal asserted every time there is a > single packet in the FIFO? Ideas?
From: heinerlitz on 30 Nov 2007 03:44 Hi Peter, we are using Virtex4 FX devices. The FIFO runs at 100 MHz and was generated with coregen 3.5. We just found out that there have been several modifications regarding the almost empty signal in coregen 4.2. We'll try that out first. Point is we NEED an almost empty signal at threshold == 1 which we can rely on 100%. If I understand you correctly this is not given with the Xilinx sync FIFOs so we would have to build our own, right? regards, Heiner On Nov 29, 5:35 pm, Peter Alfke <al...(a)sbcglobal.net> wrote: > On Nov 29, 3:46 am, "heinerl...(a)googlemail.com" > > <heinerl...(a)googlemail.com> wrote: > > Hi, > > > we are using an asynchronous FIFO to bridge two clock domains. Both > > domains have "the same" clock speed but different clock oscillators. > > > We shift data phits in the FIFO which always form a data packet. In > > between a packet data is shifted in continously without a break. > > Breaks (no shift in) are only allowed in between packets. > > On the output side of the FIFO we need a steady data stream during a > > data packet. The packet may not be interrupted. As the input side may > > be slower we start shift-out data if at least two data phits are in > > the FIFO. As the 2 clocks have almost the same frequency this > > guarantees that we never have a buffer underflow. > > > The problem we found is that the almost empty flag is only asserted if > > the FIFO is beeing emptied and not if it is beeing filled. So if the > > FIFO was empty and we get a shift in the almost empty is not asserted > > although we set the treshold to one. Is this a bug? > > Which FPGA family, which type of FIFO controller, and also what clock > rate? > Peter Alfke, Xilinx Applications> > > > We tried to solve that problem by generating a delay-empty signal at > > the output which guarantees that if the FIFO was emtpy and than > > receives a shift in we still wait another cycle so we get another > > shift in to avoid underflow. > > > This solution however does not solve the problem if the FIFO exactly > > had one entry when starting to shift out a packet. In this case > > neither delayed-empty nor almost empty is asserted, hence we get an > > underflow. > > > Why isn't the almost empty signal asserted every time there is a > > single packet in the FIFO? Ideas?
From: Peter Alfke on 30 Nov 2007 10:02
On Nov 30, 12:44 am, "heinerl...(a)googlemail.com" <heinerl...(a)googlemail.com> wrote: > Hi Peter, > > we are using Virtex4 FX devices. The FIFO runs at 100 MHz and was > generated with coregen 3.5. We just found out that there have been > several modifications regarding the almost empty signal in coregen > 4.2. We'll try that out first. > > Point is we NEED an almost empty signal at threshold == 1 which we can > rely on 100%. If I understand you correctly this is not given with the > Xilinx sync FIFOs so we would have to build our own, right? > > regards, Heiner > > On Nov 29, 5:35 pm, Peter Alfke <al...(a)sbcglobal.net> wrote: > > > On Nov 29, 3:46 am, "heinerl...(a)googlemail.com" > > > <heinerl...(a)googlemail.com> wrote: > > > Hi, > > > > we are using an asynchronous FIFO to bridge two clock domains. Both > > > domains have "the same" clock speed but different clock oscillators. > > > > We shift data phits in the FIFO which always form a data packet. In > > > between a packet data is shifted in continously without a break. > > > Breaks (no shift in) are only allowed in between packets. > > > On the output side of the FIFO we need a steady data stream during a > > > data packet. The packet may not be interrupted. As the input side may > > > be slower we start shift-out data if at least two data phits are in > > > the FIFO. As the 2 clocks have almost the same frequency this > > > guarantees that we never have a buffer underflow. > > > > The problem we found is that the almost empty flag is only asserted if > > > the FIFO is beeing emptied and not if it is beeing filled. So if the > > > FIFO was empty and we get a shift in the almost empty is not asserted > > > although we set the treshold to one. Is this a bug? > > > Which FPGA family, which type of FIFO controller, and also what clock > > rate? > > Peter Alfke, Xilinx Applications> > > > > We tried to solve that problem by generating a delay-empty signal at > > > the output which guarantees that if the FIFO was emtpy and than > > > receives a shift in we still wait another cycle so we get another > > > shift in to avoid underflow. > > > > This solution however does not solve the problem if the FIFO exactly > > > had one entry when starting to shift out a packet. In this case > > > neither delayed-empty nor almost empty is asserted, hence we get an > > > underflow. > > > > Why isn't the almost empty signal asserted every time there is a > > > single packet in the FIFO? Ideas? |