Atmel AVR assembler
in [ASM]
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From: Colin Paul Gloster on 12 Aug 2005 06:18 Herbert Kleebauer asked in news:42E27637.20DF264A(a)unibwm.de timestamped Sat, 23 Jul 2005 18:54:16 +0200: "[..] [..] Are there AVR versions which have support for hardware breakpoints[..]? [..]" Yes.
From: Colin Paul Gloster on 12 Aug 2005 07:37 Herbert Kleebauer wrote in news:42E4A9FF.2C21A3E9(a)unibwm.de timestamped Mon, 25 Jul 2005 10:59:43 +0200: "[..] If the assembly language would be well designed, we neither had registers (r0-r31) nor an IO address space. A simple "move adr1,adr2" would be sufficient. Depending on the given address, the the assembler would generate the correct opcode. But from a marketing point of view it is much better to say, AVR has 32 registers and a separate IO address space than say it correctly: AVR doesn't have any registers and we have to use a part of the memory address space for addressing the IO registers and all the ALU operations like add, and, or, ... are restricted to the first 32 memory locations (or if immediate operands are used to the memmory locatioons 16-31). The sad thing is, that because of this marketing trick we have to use a bad assembler syntax. [..]" AVRs do have registers. Performing arithmetic on values stored only in registers is quicker than performing arithmetic on values needed from RAM or ROM.
From: Herbert Kleebauer on 12 Aug 2005 15:22 Colin Paul Gloster wrote: > Herbert Kleebauer wrote in news:42E4A9FF.2C21A3E9(a)unibwm.de > If the assembly language would be well designed, we neither > had registers (r0-r31) nor an IO address space. A simple > "move adr1,adr2" would be sufficient. Depending on the > given address, the the assembler would generate the > correct opcode. > AVRs do have registers. Performing arithmetic on values stored only > in registers is quicker than performing arithmetic on values needed > from RAM or ROM. It is only an implementation detail whether the so called "registers" are implemented as FlipFlops or as the first part of the onchip SRAM. The AVR architecture doesn't have registers (an architecture is independent of the actual implementation and an assembler is architecture specific but not implementation specific). The AVR "registers" are memory mapped as is the IO.
From: Tauno Voipio on 13 Aug 2005 04:29 Herbert Kleebauer wrote: > Colin Paul Gloster wrote: > >>Herbert Kleebauer wrote in news:42E4A9FF.2C21A3E9(a)unibwm.de > > > >>If the assembly language would be well designed, we neither >>had registers (r0-r31) nor an IO address space. A simple >>"move adr1,adr2" would be sufficient. Depending on the >>given address, the the assembler would generate the >>correct opcode. > > > > >>AVRs do have registers. Performing arithmetic on values stored only >>in registers is quicker than performing arithmetic on values needed >>from RAM or ROM. > > > It is only an implementation detail whether the so called "registers" > are implemented as FlipFlops or as the first part of the onchip SRAM. > The AVR architecture doesn't have registers (an architecture is > independent of the actual implementation and an assembler is architecture > specific but not implementation specific). The AVR "registers" are memory > mapped as is the IO. The registers are imaged in low memory addresses, but there is an important difference: most operations can use registers only. The plain memory locations can be used with loads and stores only. Please check again a good reference book on RISC computer architectures. -- Tauno Voipio tauno voipio (at) iki fi
From: Herbert Kleebauer on 13 Aug 2005 07:23
Tauno Voipio wrote: > Herbert Kleebauer wrote: > The registers are imaged in low memory addresses, > but there is an important difference: most operations > can use registers only. The plain memory locations can > be used with loads and stores only. That's why I wrote: But from a marketing point of view it is much better to say, AVR has 32 registers and a separate IO address space than say it correctly: AVR doesn't have any registers and we have to use a part of the memory address space for addressing the IO registers and all the ALU operations like add, and, or, ... are restricted to the first 32 memory locations (or if immediate operands are used to the memory locations 16-31). The sad thing is, that because of this marketing trick we have to use a bad assembler syntax. The AVR architecture allows an implementation with separate registers but can also implemented as a register less CPU with ALU operations restricted to the first 32 memory locations. I wouldn't be surprised if there are low cost versions (with a lower clock speed) which don't have hardware registers. But as I said, this are implementation details, the AVR architecture uses memory mapped "registers" and therefore no registers (and no IO instructions) are necessary in an AVR assembler. > Please check again a good reference book on > RISC computer architectures. The fundamental characteristic of a RISC architecture is, that only load/store instruction can access memory. In the AVR architecture all ALU operation are performed on the first 32 memory locations. Therefore I wouldn't call the AVR architecture a RISC architecture. It is a register less architecture with a short addressing mode for the zero page. Which RISC processors do you know, which have a memory mapped register set? |