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From: KJ on 20 Nov 2009 19:31
On Nov 20, 4:12 pm, Test01 <cpan...(a)yahoo.com> wrote:
> On Nov 19, 10:08 pm, KJ <kkjenni...(a)sbcglobal.net> wrote:
>
> Hi Kevin
>
> Thanks for providing lots of good information.  You mention that
> Avalon-ST to Avalon-MM interface should be fairly straight forward.
> The thing that is confusing me is that the ST bus is packet based.
> For example, ST bus drive complete PCIe TLP packet.  These packets
> contain PCIe protocol specific information.  For example if it is a
> command request then it contains the tag, requester ID.  Thus I see
> the command on ST bus form PCIe hatrdIP, I need to process the
> response that has some the attributes of the request - response may
> need to contain the tag used on the corresponding request (as per my
> understanding).  

None of what you described has anything to do with either Avalon
streaming transfers or Avalon memory mapped interfaces...those
interfaces are simply the protocols for passing data.

> But if we use the Avalon-MM bus then all that is
> transparent. Is that true?  

Transparent to what? If the PCIe core really does need you to
"...process the
response that has some the attributes of the request - response may
need to contain the tag used on the corresponding request (as per my
understanding)" then you're completely mistaken if you think that
Avalon (or any other bus interface) will take care of any of that for
you.

> Avalon-MM bus master from HardIP side will
> issue address/data/command and then the slave device will respond to
> but the slave does not need to track the response with corresponding
> tag and other fileds.  

OK

> Is this not done by Avalon-ST to Avalon-MM
> bridge?
>

No. Bus interfaces don't give a hoot about what data is being
transferred. They exist to give a common framework for transferring
data. What data gets transferred, what higher level protocols get put
on top of that is not relevant. That's like wondering if the
specifications for to wire a building will somehow make the Ethernet,
TCP, IP protocols transparent...it won't...it's just wire.

> I would like to use the Avalon-ST but I am trying to figure out how to
> interpret the Avalon-ST packets coming out of the PCIe hard IP.
>

Now we get to the real problem and it has nothing to do with ST or
MM. Since I haven't looked at the PCIe core though I can't help you
out in interpreting the data that is coming and going, I was only
helping with the handshake protocol of ST and MM.

> The Avalon ST interface that is coming from the Stratix4GX PCIe hard
> IP. I do not have enough understanding on this so I am not sure whom
> to ask about this.

The manual for the core is a good start.

Kevin Jennings
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