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From: rickman on 16 Mar 2010 23:59
On Mar 16, 9:04 am, Andy <jonesa...(a)comcast.net> wrote:
> Though it won't help with signed/unsigned issues, you may also want to
> look at the fixed point package. It automatically promotes result
> sizes to maintain accuracy for multiplication, addision and
> subtraction. You can use it for "integer" math by simply specifying
> your LSB index at 0. The idea is that intermediate result or operand
> resizing is not usually needed with fixed point, just a final resize
> prior to storage (like the implied resize that happens with integers).
>
> I really wish they had gone the extra step to make ufixed - ufixed =
> sfixed, but alas, that did not happen (not that it would be an issue
> in your problem). With that, we'd have 99% of the flexibility of
> integers (automatic signed and size promotion), with virtually
> unlimited data sizes, at reduced simulation performance (compared to
> integer, not signed/unsigned).
> Andy

Actually, after converting the calculation to signed/unsigned types,
it was still pretty groady, so I changed it back to integer and split
it up. I need to optimize this design for size and I find that easier
if I separate the arithmetic functions so I can more easily see how
they are being implemented.

I had originally used integer because it make the calculations easy,
but doubted that this was the best way to express the calculations
because of the mess of converting the inputs from signed/unsigned and
back. As it turned out mixing signed and unsigned is still pretty
messy.

Rick
From: jacko on 17 Mar 2010 11:33
Looks like a phase controlled DCO. Maybe the frequency/phase d/dt fm
effect can be used? It does look messy, modulus if its a power of 2
should be easy to remove by a (x downto y) subrange select. If modulus
is n/(n-1) then consider MASH or bitstream delta sigma. OR use a fixed
point overflow clock gating. Has anyone ever tried n/(n-2) via up/down
clock gating of an n divider??

Cheers Jacko
From: rickman on 19 Mar 2010 10:25
On Mar 17, 11:33 am, jacko <jackokr...(a)gmail.com> wrote:
> Looks like a phase controlled DCO. Maybe the frequency/phase d/dt fm
> effect can be used? It does look messy, modulus if its a power of 2
> should be easy to remove by a (x downto y) subrange select. If modulus
> is n/(n-1) then consider MASH or bitstream delta sigma. OR use a fixed
> point overflow clock gating. Has anyone ever tried n/(n-2) via up/down
> clock gating of an n divider??
>
> Cheers Jacko

Gating (or enabling actually) a divider to adjust a clock rate will
give you the average rate you need, but it results in a jitter about
equal to the output clock period, i.e. 100%. Using a DCO results in
an output jitter equal to one reference clock period.

In my DCO the modulus is a power of two and there is no need to do
anything with the range. When the counter reaches its max count of
2^n-1 it just naturally overflows, as does unsigned arithmetic in
numeric_std. But integer arithmetic doesn't, so I have to use the mod
operator.

If you want a modulus that isn't a power of 2, you can build the
counter so it loads modulus-1 and counts down giving a carry out at
0. I knew I had no need to use a modulus that wasn't a power of two,
so I wrote the code without considering that.

Rick
From: jacko on 22 Mar 2010 08:23
True. Reducing jitter does need a higher clock speed. and a stable
power supply.
From: rickman on 22 Mar 2010 13:20
On Mar 22, 8:23 am, jacko <jackokr...(a)gmail.com> wrote:
> True. Reducing jitter does need a higher clock speed. and a stable
> power supply.

Yes, without that stable power supply, your lsbs might get lost in the
digital noise...

what???

Rick
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