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From: Vivek Menon on 19 May 2010 15:17
I am running a design using Xilinx ISE 10.1 on a 64-bit machine and
after the compilation process I see this error in the ISIM window:

Block Memory Generator data initialization complete.
Signal SIGSEGV received
ERROR: In process BLK_MEM_GEN_V2_8.I948.10
Signal SIGSEGV received

This happens only on a 64-bit machine.

Any reasons or suggestions ??
From: Brian Drummond on 19 May 2010 20:17
On Wed, 19 May 2010 12:17:40 -0700 (PDT), Vivek Menon
<vivek.menon79(a)gmail.com> wrote:

>I am running a design using Xilinx ISE 10.1 on a 64-bit machine and
>after the compilation process I see this error in the ISIM window:
>
>Block Memory Generator data initialization complete.
>Signal SIGSEGV received
>ERROR: In process BLK_MEM_GEN_V2_8.I948.10
>Signal SIGSEGV received
>
>This happens only on a 64-bit machine.
>
>Any reasons or suggestions ??

ISIM in ISE10 has many ways to crash with a SIGSEGV.
Unfortunately the only way to find the problem is to remove one block at
a time from your design until it stops crashing, then put that block
back in and comment out bits of it until you find the cause.

Any constructs that are even slightly unusual in your code, are possible
candidates for the crash. Once you find it, it is usually easy to work
around the problem.

Returning access types from functions (workaround: pass them as
OUTparameters from a procedure), type conversions in port maps
(workaround: use intermediate signals), and connecting INOUT ports from
VHDL to a Verilog component are just a few of the causes I have seen.

A lot of them have been fixed in ISE 11, so the easiest option might be
to upgrade to ISE11 or 12.

- Brian
From: Vivek Menon on 19 May 2010 20:58
On May 19, 8:17 pm, Brian Drummond <brian_drumm...(a)btconnect.com>
wrote:
> On Wed, 19 May 2010 12:17:40 -0700 (PDT), Vivek Menon
>
> <vivek.meno...(a)gmail.com> wrote:
> >I am running a design using Xilinx ISE 10.1 on a 64-bit machine and
> >after the compilation process I see this error in the ISIM window:
>
> >Block Memory Generator data initialization complete.
> >Signal SIGSEGV received
> >ERROR: In process BLK_MEM_GEN_V2_8.I948.10
> >Signal SIGSEGV received
>
> >This happens only on a 64-bit machine.
>
> >Any reasons or suggestions ??
>
> ISIM in ISE10 has many ways to crash with a SIGSEGV.
> Unfortunately the only way to find the problem is to remove one block at
> a time from your design until it stops crashing, then put that block
> back in and comment out bits of it until you find the cause.
>
> Any constructs that are even slightly unusual in your code, are possible
> candidates for the crash. Once you find it, it is usually easy to work
> around the problem.
>
> Returning access types from functions (workaround: pass them as
> OUTparameters from a procedure), type conversions in port maps
> (workaround: use intermediate signals), and connecting INOUT ports from
> VHDL to a Verilog component are just a few of the causes I have seen.
>
> A lot of them have been fixed in ISE 11, so the easiest option might be
> to upgrade to ISE11 or 12.
>
> - Brian

Will try compiling modules separately and debug
Upgrading to 11 or 12 is not an option.
I tried going through the answer records on xilinx for Block Memory
Generator v2.8 and could not find any solutions.
I don't understand how the BLK_MEM_GEN v2.8 can fail for the 64 bit
machine? Something to do with the global values?
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