CPLD programming sequence XC9500
in [FPGA]
|
From: gopal_amlekar on 16 Jan 2010 07:29 Hello, I want to understand a few things about CPLD programming. There is a configuration sequence followed for FPGA. For e.g. XAPP188 Table 7 on page 11 shows the device configuration sequence to transfer a bit stream. Similarly, is there any sequence for CPLD XC9500? What I understood is that the .jed file is transferred instead of .bit file in the SHIFT-DR state. Is this correct? After transferring the .jed file does XC9500 also need the JSTART instruction and switching to Run-Test-Idle state? Is the entire .jed file transferred or there is some header or similar information which is skipped? Also, how to read the Device IDCODE of the CPLD? How to issue the IDCODE instruction? Thanks for support... --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
From: Uwe Bonnes on 16 Jan 2010 08:23 gopal_amlekar <gopal_amlekar(a)n_o_s_p_a_m.yahoo.com> wrote: > Hello, > I want to understand a few things about CPLD programming. > There is a configuration sequence followed for FPGA. For e.g. XAPP188 Table > 7 on page 11 shows the device configuration sequence to transfer a bit > stream. > Similarly, is there any sequence for CPLD XC9500? > What I understood is that the .jed file is transferred instead of .bit file > in the SHIFT-DR state. Is this correct? > After transferring the .jed file does XC9500 also need the JSTART > instruction and switching to Run-Test-Idle state? > Is the entire .jed file transferred or there is some header or similar > information which is skipped? > Also, how to read the Device IDCODE of the CPLD? How to issue the IDCODE > instruction? The .jed describes a bitmap.The jedecfilehas to be interpreted first into a bitmap. The bitmap is then transfered in a complicated way into the CPLD. The procedures are described somehow in the 1532 Jedec files, in the files found when searching XILINX.com with "algorithm jedec" ("Device Programming Specification"). xc3sprog on sourceforge implements a reader for jedecfiles and and a XC95X(L|V) programmer with these documents and the sources found in the last naxjp version with sources (naxjp-079). Read the documents and the sources http://sourceforge.net/projects/xc3sprog/develop to understand what's going on. B.t.w., for the Coolrunner 2 the Jedecfile describes the bits in a logical order and before transfering in the XC3C CPLD the bits have to be scrambled in physical order with .map files for the appropriate device found in the Xilinx ISE/xbr/data folder. For basic JTAG experiments , start at www.fpga4fun.com/JTAG.html Bye -- Uwe Bonnes bon(a)elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
From: Uwe Bonnes on 16 Jan 2010 08:29 gopal_amlekar <gopal_amlekar(a)n_o_s_p_a_m.yahoo.com> wrote: > Hello, > I want to understand a few things about CPLD programming. > There is a configuration sequence followed for FPGA. For e.g. XAPP188 Table > 7 on page 11 shows the device configuration sequence to transfer a bit > stream. > Similarly, is there any sequence for CPLD XC9500? > What I understood is that the .jed file is transferred instead of .bit file > in the SHIFT-DR state. Is this correct? > After transferring the .jed file does XC9500 also need the JSTART > instruction and switching to Run-Test-Idle state? > Is the entire .jed file transferred or there is some header or similar > information which is skipped? > Also, how to read the Device IDCODE of the CPLD? How to issue the IDCODE > instruction? The .jed describes a bitmap.The jedecfile has to be interpreted first into a bitmap. The bitmap is then transfered in a complicated way into the CPLD. The procedures are described somehow in the 1532 Jedec files and in the files found when searching XILINX.com with "algorithm jedec" ("Device Programming Specification"). xc3sprog on sourceforge implements a reader for jedecfiles and a XC95X(L|V) programmer with these documents and the sources found in the last naxjp version with sources (naxjp-079). Read the documents and the sources http://sourceforge.net/projects/xc3sprog/develop to understand what's going on. B.t.w., for the Coolrunner 2 the Jedecfile describes the bits in a logical order and before transfering in the XC2C CPLD the bits have to be scrambled in physical order with .map files for the appropriate device found in the Xilinx ISE/xbr/data folder. For basic JTAG experiments , start at www.fpga4fun.com/JTAG.html Bye -- Uwe Bonnes bon(a)elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
|
Pages: 1 Prev: Altera Quartus II on Debian GNU/Linux Next: Simulation of VHDL code for a vending machine |