CPU design
in [FPGA]
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From: Frank Buss on 24 Aug 2006 02:44 jacko wrote: > AHDL for a two register NOP, INC, DEC, WRITE unit > > http://indi.joox.net link to quartus II files, BIREGU.bdf > > good for interruptable stack pointers This looks like a net list or something like this. I have only ISE WebPack installed and I don't know how to display it. Do you have a picture of it? -- Frank Buss, fb(a)frank-buss.de http://www.frank-buss.de, http://www.it4-systems.de
From: Walter Banks on 29 Aug 2006 13:08 Jim, We have certainly thought about it. Byte Craft has done quite a bit of instruction design work on embedded commercial processors. Internally for every C compiler we create an instruction set simulator with a lot of performance instrumentation. I expect the next round of processors will move towards multiple processor solutions to applications. Compilers and other HLL tools will be focused on application work division. w.. Jim Granville wrote: > Walter Banks wrote: > > > > > Interrupts can be removed at extremely low cost to applications. Both the > > Microchip PIC12 and Freescale RS08 do not have interrupts. In the > > RS08 C compiler we developed some software IP to where possible > > go into a power down mode and launch execution threads that compiled as > > execution to completion. > > > > The threads are typically short and a as a side effect run to completion > > makes local re-use easy > > > > C compilers implemented for small processors work well with out either > > a data or subroutine return stack. Two of the processors we have written > > compilers for in the last couple years both used an assessable return > > register. Flow control analysis in the compiler make nested subroutines > > user transparent. > > > > The instruction set reduction in the RS08 from the S08 parent had a > > 4-6% impact on application performance. > > > > Walter.. > > Hi Walter, > Have you ever thought about doing a Compiler+FPGA_CPU (+Sim+Debug?) > bundle ? > > -jg
From: Jim Granville on 29 Aug 2006 17:49 Walter Banks wrote: > Jim, > > We have certainly thought about it. Byte Craft has done quite a bit of > instruction design work on embedded commercial processors. Internally > for every C compiler we create an instruction set simulator with a lot of > performance instrumentation. > > I expect the next round of processors will move towards multiple processor > solutions to applications. Compilers and other HLL tools will be focused on > application work division. > > w.. Sounds promising. What about debug pathways ? -jg
From: Walter Banks on 30 Aug 2006 14:40 Jim, The automotive processors use a separate communication link (most are on board packet switched virtual links) to each processor brought out through a interface on the chip. (Nexus) There are support standards for this. The asian processors that we have created support for were lockstepped simulation and hardware to extract more information for the developers. Most of the current processors that I am seeing are using asynchronous background BDM or JTAG brought out through a limited number of pins. Watch this space later in the year for information on the consumer products multiprocessor debug support. w.. Jim Granville wrote: > Walter Banks wrote: > > Jim, > > > > We have certainly thought about it. Byte Craft has done quite a bit of > > instruction design work on embedded commercial processors. Internally > > for every C compiler we create an instruction set simulator with a lot of > > performance instrumentation. > > > > I expect the next round of processors will move towards multiple processor > > solutions to applications. Compilers and other HLL tools will be focused on > > application work division. > > > > w.. > > Sounds promising. What about debug pathways ? > > -jg
From: jacko on 31 Aug 2006 21:30
Frank Buss wrote: > jacko wrote: > > > > > http://indi.joox.net link to quartus II files > > This looks like a net list or something like this. I have only ISE WebPack > installed and I don't know how to display it. Do you have a picture of it? i think ahdl custom to altera. there tool is web downloaded. could notget the xilinx tool to download after 5 attempts. website more specific. the zip file is current project design files in quartus II version 6, but still have to design instruction sequencing unit. thought of using an 8 cycle simple instruction execution, for a very compact IP core. also decided that modular forth in instancable blocks would be most flexible. it is going to evolve as a 16n design, as all carry can happen along multiple instances to make any 16*n word size, but i have to decide how the program word width may or may not expand to the word size. i hope to get wishbone and avalon bus interfaces too, but this is not my immediate priority. i intend a serial bus standard to allow connected multicore designs, each core having 128KB memory. does anyone know how to export a quartus project as VHDL? cheesr jacko |