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From: ivan@gmail.com on 24 Oct 2006 04:17
Thanks a lot, I am using VHDL and Xilinx XC2V1000. However because of
lack number of I/O pins (I only have 30 pins for this purpose, because
before it was designed to get image directly form camera and a little
bit surprised when it come to me with PCMCIA framegrabber). Right now I
am thinking to use small CPLD or FPGA only for camera. Now I am
understand how to get the image data, but still have question about
camera control. Does somebody know the signal that needs to be sent to
controll the camera ?

Again, thank you very much for all your help.

-ivan



Brad Smallridge wrote:
> > The document which I found mostly only dealed with the pin
> > configuration and didn't tell how to obtain the image pixel. I plan to
> > use DS90CR288A to convert from LVDS to parallel. After that I don't
> > know what should I do with parallel signal.
>
> After you use that chip, the data should be available on certain
> lines, if it's a "base" configuration:
>
> camdat:process(clk)
> begin
> if( clk'event and clk='1') then
> -- eight bit output
> camdat_out(0) <= '0';
> camdat_out(1) <= cam_in(0);
> camdat_out(2) <= cam_in(1);
> camdat_out(3) <= cam_in(2);
> camdat_out(4) <= cam_in(3);
> camdat_out(5) <= cam_in(4);
> camdat_out(6) <= cam_in(6);
> camdat_out(7) <= cam_in(27);
> camdat_out(8) <= cam_in(5);
> -- twelve bit output
> -- camdat_out(0) <= cam_in(3);
> -- camdat_out(1) <= cam_in(4);
> -- camdat_out(2) <= cam_in(6);
> -- camdat_out(3) <= cam_in(27);
> -- camdat_out(4) <= cam_in(5);
> -- camdat_out(5) <= cam_in(7);
> -- camdat_out(6) <= cam_in(8);
> -- camdat_out(7) <= cam_in(9);
> -- camdat_out(8) <= cam_in(12);
> -- testoutput
> -- camdat_out <= cam_col_count;
> end if;
> end process;
>
> You didn't say what language or chip you are using.
>
> Brad Smallridge
> aivision

From: Gabor on 25 Oct 2006 09:02

ivan(a)gmail.com wrote:
> Thanks a lot, I am using VHDL and Xilinx XC2V1000. However because of
> lack number of I/O pins (I only have 30 pins for this purpose, because
> before it was designed to get image directly form camera and a little
> bit surprised when it come to me with PCMCIA framegrabber). Right now I
> am thinking to use small CPLD or FPGA only for camera. Now I am
> understand how to get the image data, but still have question about
> camera control. Does somebody know the signal that needs to be sent to
> controll the camera ?
>
> Again, thank you very much for all your help.
>
> -ivan

The standard method to control the camera via Camera Link uses
asynchronous serial communication at 9600 baud, 8-bits, no parity,
1 stop bit. Camera manufacturers generally either publish their
protocol or supply control software that can be integrated with
any framegrabber using a standard Camera Link serial communication
..dll file. The serial link uses LVDS levels, and is called SERTFG for
"serial to framegrabber" and SERTC for "serial to camera" to avoid
confusion associated with the standard TxD and RxD naming. Some
camera manufacturers offer a .dll file to use a standard PC serial
port,
which will allow you to get the control program running with the least
software effort. In this case you just need to have hardware to
translate
the serial (COMM port) from the PC from RS-232 to LVDS.

HTH,
Gabor

From: Gabor on 25 Oct 2006 09:06

Guru wrote:
> Why do you want to use a separate chip for LVDS to paralell? Is the
> frequency too high? Spartan3 (or other) has LVDS integrated in IOB.
>
> Cheers,
>
> Guru

I wouldn't recommend this with the Virtex 2 series. The Camera Link
uses "Channel-Link" 7:1 serializers. The DCM does not do a very good
job of multiplying the input clock by 7. Also the frequency at the
individual serial inputs can be as much as 85MHz * 7 = 595 MHz,
so there isn't a lot of room for jitter on the sampling clock,
especially
if you consider the maximum allowed skew over the cable from the
camera.

just my 2 cents,
Gabor

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