From: Kappa on
Hi,

I have write simple lockup table:

#################### [CODE] ####################

din : in std_logic_vector (3 downto 0);
dout : out std_logic_vector (1 downto 0)

begin

process(din)
begin
case(din) is
when "000" => dout <= conv_std_logic_vector(2, 2);
when "001" => dout <= conv_std_logic_vector(0, 2);
when "010" => dout <= conv_std_logic_vector(1, 2);
when "011" => dout <= conv_std_logic_vector(1, 2);
when "100" => dout <= conv_std_logic_vector(2, 2);
when "101" => dout <= conv_std_logic_vector(3, 2);
when "110" => dout <= conv_std_logic_vector(3, 2);
when "111" => dout <= conv_std_logic_vector(0, 2);
when others => null;
end case;
end process;

#################### [/CODE] ####################

But I want to write values in HEX format example:

#################### [CODE] ####################

din : in std_logic_vector (3 downto 0);
dout : out std_logic_vector (1 downto 0)

begin

process(din)
begin
case(din) is
when x"0" => dout <= x"2";
when x"1" => dout <= x"0";
when x"2" => dout <= x"1";
when x"3" => dout <= x"1";
when x"4" => dout <= x"2";
when x"5" => dout <= x"3";
when x"6" => dout <= x"3";
when x"7" => dout <= x"0";
when others => null;
end case;
end process;

#################### [/CODE] ####################

But with this format i obtain an error ...

"String literal "0000" is of size 4 but is expected to be of size 3."

VHDl x"--" generate bit_vector, but how limit number of bit ?

Thanks.

secureasm
From: John_H on
On Apr 7, 9:56 am, Kappa <secure...(a)gmail.com> wrote:
>
> #################### [/CODE] ####################
>
> But with this format i obtain an error ...
>
> "String literal "0000" is of size 4 but is expected to be of size 3."
>
> VHDl x"--" generate bit_vector, but how limit number of bit ?
>
> Thanks.
>
> secureasm

Two choices from my perspective: use Octal instead of heX (O"6")
introduced in VHDL-1993 or extend the case value din to 4 bits with
concatenation.

The one url I grabbed for the VHDL-1993 reference (http://
www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_ease/)
mentions:

"One limitation in VHDL-1993 is that hexadecimal bit-string literals
always contain a multiple of 4 bits, and octal ones a multiple of 3
bits. You can’t have a 10-bit hexadecimal bit-string literal, or one
containing values other than 0, 1 or _, for example."
From: Gabor on
On Apr 7, 10:55 am, John_H <newsgr...(a)johnhandwork.com> wrote:
> On Apr 7, 9:56 am, Kappa <secure...(a)gmail.com> wrote:
>
>
>
> > #################### [/CODE] ####################
>
> > But with this format i obtain an error ...
>
> > "String literal "0000" is of size 4 but is expected to be of size 3."
>
> > VHDl x"--" generate bit_vector, but how limit number of bit ?
>
> > Thanks.
>
> > secureasm
>
> Two choices from my perspective: use Octal instead of heX (O"6")
> introduced in VHDL-1993 or extend the case value din to 4 bits with
> concatenation.
>
> The one url I grabbed for the VHDL-1993 reference (http://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_ease/)
> mentions:
>
> "One limitation in VHDL-1993 is that hexadecimal bit-string literals
> always contain a multiple of 4 bits, and octal ones a multiple of 3
> bits. You can’t have a 10-bit hexadecimal bit-string literal, or one
> containing values other than 0, 1 or _, for example."

The error message strangely does not match the declared size of
din as (3 downto 0). I would have expected the original code to
have an error message...
From: Kappa on
Hi

> Two choices from my perspective: use Octal instead of heX (O"6")
> introduced in VHDL-1993 or extend the case value din to 4 bits with
> concatenation.

OK for 3 bits I use O"6" instead of X, but with 5 bits ?

> "One limitation in VHDL-1993 is that hexadecimal bit-string literals
> always contain a multiple of 4 bits, and octal ones a multiple of 3
> bits. You can’t have a 10-bit hexadecimal bit-string literal, or one
> containing values other than 0, 1 or _, for example."

If I can't have 10 bits then not even 5 bits ?

Thanks.

secureasm

From: John_H on
On Apr 7, 11:57 am, Kappa <secure...(a)gmail.com> wrote:
> Hi
>
> > Two choices from my perspective: use Octal instead of heX (O"6")
> > introduced in VHDL-1993 or extend the case value din to 4 bits with
> > concatenation.
>
> OK for 3 bits I use O"6"  instead of X, but with 5 bits ?
>
> > "One limitation in VHDL-1993 is that hexadecimal bit-string literals
> > always contain a multiple of 4 bits, and octal ones a multiple of 3
> > bits. You can’t have a 10-bit hexadecimal bit-string literal, or one
> > containing values other than 0, 1 or _, for example."
>
> If I can't have 10 bits then not even 5 bits ?
>
> Thanks.
>
> secureasm

Maybe you'd do better with VHDL-2008?

Perhaps you could take the suggestion of concatenating your case
variable to get a multiple of 4 bits so it evens out with the compare.