Prev: EDK : *.bit and *.elf Files
Next: Embedded clocks
From: homoalteraiensis on 5 Aug 2006 17:18
I still discover a difference between the fmax for Cyclone I and
Cyclone II.

Is this caused by the DP-RAM bug with Cyclone II devices -
let's say with the additional hardware produced by the work around?

From: Martin Schoeberl on 6 Aug 2006 05:19
>I still discover a difference between the fmax for Cyclone I and
> Cyclone II.
>
> Is this caused by the DP-RAM bug with Cyclone II devices -
> let's say with the additional hardware produced by the work around?
>
AFAIK the example I'm using (same data width on both ports)
does not need the additional hardware. With different port
widths, which I used first, I got the additional MUX inserted
by Quartus. However, in my application I can tolerate some
latency, so I will MUX the data (and demux) it in an extra
pipeline stage.

Martin


First  |  Prev  | 
Pages: 1 2
Prev: EDK : *.bit and *.elf Files
Next: Embedded clocks