DCM

Prev: CDMA ON FPGA
Next: bit vs std_logic (was Re: Simulation of VHDL code for a vending machine)

From: abhishek kumar on 18 Jan 2010 01:15

---

Sir,
I am designing DLL using DCM on VERTEX4. But I am not gwtting
output for clk2x, clk2x180 I am giving my code below. I am not able to
find whetre is the fault. I have written this code in architecture
code, I didn't use coreIP where generates .xaw file .
I tried that too but not got expected result ?


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_dll is
Port ( sys_clk,reset_in : in STD_LOGIC;

fpga_clk,fpga_clk2x,clk90_out,clk180_out,clk270_out,locked_out : out
STD_LOGIC);
end clk_dll;

architecture Behavioral of clk_dll is
signal
clk0_buf,clk90_buf ,clk180_buf,clk270_buf,clk_fb_in,clk0a,clk2x_buf:std_logic;
component IBUFG
port (
O : out std_logic;
I : in std_logic
);
end component;

Component BUFG
port (
O : out std_logic;
I : in std_logic );
end component;

component DCM_BASE
port (
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
CLKIN : in std_logic;
CLKFB : in std_logic;
RST : in std_logic );
end component;


begin
ibuf0:ibufg port map(i=>sys_clk,o=>clk0a);
buf1: bufg port map (i=> clk0_buf, o=> clk_fb_in);




dll: DCM_BASE port map (CLKIN => clk0a, CLKFB => Clk_FB_in, RST =>
Reset_in, CLK0 => Clk0_buf,
CLK90 => clk90_buf, CLK180 => clk180_buf, CLK270 =>
clk270_buf, CLK2X => clk2x_buf, CLK2X180 => OPEN,
CLKDV => open, CLKFX => OPEN, CLKFX180 => OPEN, LOCKED =>
locked_out);

fpga_clk<=clk_fb_in;
buf2:bufg port map(i=>clk90_buf,o=>clk90_out);
buf3:bufg port map(i=>clk180_buf,o=>clk180_out);
buf4:bufg port map(i=>clk270_buf,o=>clk270_out);
buf5:bufg port map(i=>clk2x_buf,o=>fpga_clk2x);
end Behavioral;

From: Gabor on 18 Jan 2010 08:57

---

On Jan 18, 1:15 am, abhishek kumar <abkv...(a)gmail.com> wrote:
> Sir,
>        I am designing DLL using DCM on VERTEX4. But I am not gwtting
> output for clk2x, clk2x180 I am giving my code below. I am not able to
> find  whetre is the fault. I have written this code in architecture
> code, I didn't use coreIP where generates .xaw file .
> I tried that too but not got expected result ?
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>  library UNISIM;
>  use UNISIM.VComponents.all;
> ---- Uncomment the following library declaration if instantiating
> ---- any Xilinx primitives in this code.
> --library UNISIM;
> --use UNISIM.VComponents.all;
>
> entity clk_dll is
>     Port ( sys_clk,reset_in : in  STD_LOGIC;
>
> fpga_clk,fpga_clk2x,clk90_out,clk180_out,clk270_out,locked_out : out
> STD_LOGIC);
> end clk_dll;
>
> architecture Behavioral of clk_dll is
> signal
> clk0_buf,clk90_buf ,clk180_buf,clk270_buf,clk_fb_in,clk0a,clk2x_buf:std_logic;
> component IBUFG
>  port (
>    O : out std_logic;
>    I : in std_logic
>  );
> end component;
>
> Component BUFG
>  port (
>    O : out std_logic;
>    I : in std_logic );
> end component;
>
> component DCM_BASE
>  port (
>    CLK0 : out std_logic;
>    CLK90 : out std_logic;
>    CLK180 : out std_logic;
>    CLK270 : out std_logic;
>    CLK2X : out std_logic;
>    CLK2X180 : out std_logic;
>    CLKDV : out std_logic;
>    CLKFX : out std_logic;
>    CLKFX180 : out std_logic;
>    LOCKED : out std_logic;
>    CLKIN : in std_logic;
>    CLKFB : in std_logic;
>    RST : in std_logic );
> end component;
>
> begin
> ibuf0:ibufg port map(i=>sys_clk,o=>clk0a);
> buf1: bufg port map (i=> clk0_buf, o=> clk_fb_in);
>
> dll: DCM_BASE port map (CLKIN => clk0a, CLKFB => Clk_FB_in, RST =>
> Reset_in, CLK0 => Clk0_buf,
>                         CLK90 => clk90_buf, CLK180 => clk180_buf, CLK270 =>
> clk270_buf, CLK2X => clk2x_buf, CLK2X180 => OPEN,
>                         CLKDV => open, CLKFX => OPEN, CLKFX180 => OPEN, LOCKED =>
> locked_out);
>
> fpga_clk<=clk_fb_in;
> buf2:bufg port map(i=>clk90_buf,o=>clk90_out);
> buf3:bufg port map(i=>clk180_buf,o=>clk180_out);
> buf4:bufg port map(i=>clk270_buf,o=>clk270_out);
> buf5:bufg port map(i=>clk2x_buf,o=>fpga_clk2x);
> end Behavioral;

There are a number of generics required to set up the DCM
in the correct operating mode, not the least of which is
DLL_FREQUENCY_MODE, which must be "LOW" in order to get
the 2x outputs. Look in the Virtex-4 Libraries Guide for
HDL Designs, available from the ISE help menu under
"Software Manuals." There are instantiation templates
in the manual which should help. Also refer to your
Virtex 4 data sheet to make sure your part is spec'd
to work in low frequency mode with your clock input
frequency.

HTH,
Gabor

 | 
Pages: 1
Prev: CDMA ON FPGA
Next: bit vs std_logic (was Re: Simulation of VHDL code for a vending machine)