DDR SDRAM demo for Spartan-3E starter kit? [FPGA]

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From: posedge52 on 5 Jan 2008 06:31

I have a Xilinx/Digilent Spartan-3E starter kit Rev D (with 46V32M16
-6T F).
Is there any *simple* demo that stores a picture bitmap in the builtin
DDR SDRAM and sends the bitmap to the VGA port continously ..?

Is it correct that the DDR SDRAM won't go below 75 MHz due the DLL
used ..?
(Micron indicate that SDRAM can go as low as a few kHz in clock
frequency if needed)

I had a look at 3 Xilinx examples, but they seem almost more
complicated to get running than to code a sdram controller by myself.
Currently trying out opencores controller, but it seems to get stuck
synthesis.

What voltage is Vtt supposed to have for ddr sdram?, Is every resistor
needed, or can one do with a simpler interface if the dram <-> fpga
path is less than 1 inch/2 cm ..?

From: jb on 5 Jan 2008 08:52

From: ratemonotonic on 5 Jan 2008 10:32

On 5 Jan, 11:31, posedg...(a)yahoo.com wrote:
> I have a Xilinx/Digilent Spartan-3E starter kit Rev D (with 46V32M16
> -6T F).
> Is there any *simple* demo that stores a picture bitmap in the builtin
> DDR SDRAM and sends the bitmap to the VGA port continously ..?
>
> Is it correct that the DDR SDRAM won't go below 75 MHz due the DLL
> used ..?
> (Micron indicate that SDRAM can go as low as a few kHz in clock
> frequency if needed)
>
> I had a look at 3 Xilinx examples, but they seem almost more
> complicated to get running than to code a sdram controller by myself.
> Currently trying out opencores controller, but it seems to get stuck
> synthesis.
>
> What voltage is Vtt supposed to have for ddr sdram?, Is every resistor
> needed, or can one do with a simpler interface if the dram <-> fpga
> path is less than 1 inch/2 cm ..?

I am in the process of implementing a interface between microblaze and
Micron DDR SDRAM using MPMC from the IP catalog provided in EDK 9.2i.
It has all the neccesary ports defined and support most DDR/DDR2
devices. I have not tested it yet, but it might be worth a try.

BR
rate

From: quark.flavour on 5 Jan 2008 13:14

On Jan 5, 12:31 pm, posedg...(a)yahoo.com wrote:
> I have a Xilinx/Digilent Spartan-3E starter kit Rev D (with46V32M16
> -6T F).
> Is there any *simple* demo that stores a picture bitmap in the builtin
> DDR SDRAM and sends the bitmap to the VGA port continously ..?

I've just bought the same board, and I'm interested in a DDR
controller
for the MT46V32M16. I've started coding one but I'm a novice in VHDL
and it may took a lot of time... maybe the eternity! ;)

> Is it correct that the DDR SDRAM won't go below 75 MHz due the DLL
> used ..?
> (Micron indicate that SDRAM can go as low as a few kHz in clock
> frequency if needed)

Reading at page 24 of the device datasheet (Electrical Characteristics
and
Recommended AC Operating Conditions (-6, -6T, -75E)) it looks like
the
clock cycle time must be between 6 and 13 ns, meaning that the default
board clock (50 MHz) is not enough (you can use a DCM). Note 46 says
that it works below the JEDEC slowest operating frequency of 83 MHz
(13 ns ck = 76 MHz cf). Moreover consider that you should issue an
auto
refresh command every few (6 or 7) us.

As i said I'm beginning with VHDL, I'm just learning and what I'm
writing is
something to read/write a 32 bit value from/to a specific address,
that is, I'm not
looking for performance, just to basic functionality.

Joerg's solution should be nice, I'll take a look at the Verilog code
(BTW thanks),
I don't think I'll use the MicroBlaze soft processor because it's
commercial
and I'm just having fun with the FPGA in the spare time.

Regards

Andrew

From: jb on 5 Jan 2008 15:40

On Jan 5, 7:14 pm, quark.flav...(a)gmail.com wrote:

> Joerg's solution should be nice, I'll take a look at the Verilog code
> (BTW thanks), I don't think I'll use the MicroBlaze soft processor because it's
> commercial and I'm just having fun with the FPGA in the spare time.

I ported the open source Lattice Mico32 CPU to Xilinx and Altera
chips -- Comparable
to MicroBlaze (a bit larger, and a slightly lower f_max), buts it's
cross vendor RTL code
and complete open source [1].

Works fine with the wb_ddr controller on the said boards and powers
for example
http://www.youtube.com/watch?v=4MGKhFIujM4

It's not the first complete open source SoC, and won't be the last one
-- But it's a capable
small footprint SoC plattform baeed on the wishbone interconnect. The
only thing I'm
currently really missing is a MMU.

jb

[1] https://roulette.das-labor.org/bzrtrac/wiki/soc-lm32

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