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From: Frank van Eijkelenburg on 11 Aug 2010 11:48
On Aug 3, 6:03 pm, alpha <zhg....(a)gmail.com> wrote:
> On Aug 3, 3:26 am, Frank van Eijkelenburg <fei.technolut...(a)gmail.com>
> wrote:
>
>
>
> > On Aug 2, 5:28 pm, glen herrmannsfeldt <g...(a)ugcs.caltech.edu> wrote:
>
> > > Frank van Eijkelenburg <fei.technolut...(a)gmail.com> wrote:
>
> > > > I have a custom made PCIe board with a Virtex 5 FPGA on which I
> > > > implemented aDMAunit which uses the PCIe endpoint block plus v1.14.
> > > > I also implemented simple read/write operations from the PC to the
> > > > board (the board responds with completion TLPs). The read/write
> > > > operations are working,DMAis not working (transferring data from
> > > > FPGA to PC).
>
> > > (snip)
>
> > > > When I start aDMAoperation by writing a register in the FPGA, I can
> > > > see in chipscope the correct physical addresses in the TLP header (of
> > > > the memory write requests). However, I do not see the correct values
> > > > in the allocated memory at the PC. What can I do to check where it is
> > > > going wrong?
>
> > > Not having tried to doDMAthrough PCI before, is data being
> > > written, but the wrong data?
>
> > That is what I do not know. Yes the correct data is send to the PC,
> > but if I readout the memory the values are unchanged.
>
> > > I would try writing all zeros or all ones and see if those come
> > > through fine.  It could be timing between the FPGA and PCI such
> > > that the wrong data is being latched.
>
> > > Then try slightly less predictable data and see what gets through.
>
> > > -- glen
>
> > If it was timing, I expect the other way around also problems (which I
> > don't have). Also single memory read/write requests send from the PC
> > are working correctly.
>
> Does CPU caches get snooped whenDMAwrote into host memory?  If not,
> then you may not see right data by normal read.

Finally, I solved the problem. For those who want to learn from
mistakes of others, here comes the cause of the problem:

The packets which were transmitted to the pc were too large (more than
the maximum payload size of the receiver). In that case, the packets
are simply dropped (no errors). Of course I have to read the maximum
payload size from the device control register in the PCI Express
Capability structure.

best regards,

Frank
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