Prev: EDK 11,1 on Windows 7, 32 Bit
Next: what is incorrect about my usage of array with port entity?
From: de4 on 16 Feb 2010 06:20
Please help me I have really mess in my head with titles above.
A have got custom processor that uses RAM which is created from Block
RAMs.
RAM is generated from CoreGen. I was initilizing BlockRAM's using .coe
file.
But it takes 'hours' to update code/data in .coe file and reimplement
design.
I wish to update data in .bit file without re-design. I found that there is
a tool data2mem that do that for me. But it takes .bmm files and .mem files
and this is problem for me...I don't know how to create files like this...
I have seen syntax in .bmm files and I was quite scary for me...

I'm FPGA beginner and can anybody tell me what to do in steps to create
those .bmm files and .mem files. I was searching it for few hours and I
don't catch this...

Please help and thank you for any answer...
Best Regards,
Mac


---------------------------------------
Posted through http://www.FPGARelated.com
From: de4 on 16 Feb 2010 11:14
Thank you very much, You helped me really a lot...
They should write it in datasheet as you said that.
Thanks again and I going now to fight with this

Best regards,
maciek

---------------------------------------
Posted through http://www.FPGARelated.com
From: Symon on 16 Feb 2010 07:25
http://www.xilinx.com/itp/xilinx92/books/docs/d2m/d2m.pdf

Read that. Then come back and ask questions.
HTH, Syms.
From: he on 16 Feb 2010 07:45
First you should constrain the used BRAMs to fixed locations, so you
don't have to recreate a new bmm file after each P&R run.
Most probably, you will have to write the BMM file "by hand" (see the
link posted by Symon, tell me if theres an automated way ;)
The mem-file syntax is quite simple, but there are tools to create these
mem files from binary files like srecord (srecord.sourceforge.net):
$ srec_cat bram_content.bin -binary -o ram.mem -vmem 8

hth,
HE



de4 schrieb:
> Please help me I have really mess in my head with titles above.
> A have got custom processor that uses RAM which is created from Block
> RAMs.
> RAM is generated from CoreGen. I was initilizing BlockRAM's using .coe
> file.
> But it takes 'hours' to update code/data in .coe file and reimplement
> design.
> I wish to update data in .bit file without re-design. I found that there is
> a tool data2mem that do that for me. But it takes .bmm files and .mem files
> and this is problem for me...I don't know how to create files like this...
> I have seen syntax in .bmm files and I was quite scary for me...
>
> I'm FPGA beginner and can anybody tell me what to do in steps to create
> those .bmm files and .mem files. I was searching it for few hours and I
> don't catch this...
>
> Please help and thank you for any answer...
> Best Regards,
> Mac
>
>
> ---------------------------------------
> Posted through http://www.FPGARelated.com
From: Symon on 16 Feb 2010 08:50
On 2/16/2010 12:45 PM, he wrote:
> First you should constrain the used BRAMs to fixed locations, so you
> don't have to recreate a new bmm file after each P&R run.
> Most probably, you will have to write the BMM file "by hand" (see the
> link posted by Symon, tell me if theres an automated way ;)

I dimly recall analysing the RBT format, and then writing a perl script
that searched through the RBT file for a BRAM with contents beginning
"DEADBEEF", or whatever I'd tagged the BRAM with, to automatically
update the BMM after a PAR. However, as you point out, constraining the
placement was much easier.

Cheers, Syms.
 |  Next  |  Last
Pages: 1 2 3
Prev: EDK 11,1 on Windows 7, 32 Bit
Next: what is incorrect about my usage of array with port entity?