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From: VDT153 on 10 Apr 2010 14:10
Hi,

I am working on moving an ASIC design to FPGA. For this i am using
synplify pro synthesis tool. But, the tool does not seem to recognise
all the gated clocks [sometimes because it cant recognise the base
clock].

is there any alternative method to declare the base clock for the
gated design other than using the create_clock contraint in the sdc
file.

Thanks in advance
vdt153
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