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From: Vic Orloff on 19 Jun 2010 01:10
Thank you very much!

It looks a very good list of key points to check indeed.
From: Vic Orloff on 18 Jun 2010 15:14
Hello,

I am a beginner and have tried to learn how to configure my FPGA
(XC3S1600E) in Master Serial Mode using configuration of a design
stored in Platform Flash PROM (XCF04S) .
I use Xilinx ISE 9.1i and followed the steps described in 'Spartan-3
Generation Configuration User Guide (ug332.pdf, pages 42-46 and
91-100) and everything seemed working alright - FPGA bitstream was
generated, PROM file (.mcs) for Platform Flash PROM memory was created
and PROM was successfuly programmed using JTAG ('Program Succeeded'
message appeared). So everything seems working according to the guide
but when I power board off and then on, my FPGA is not configured
according to what I have programmed into PROM.

So my problem is that although PROM is seemed correctly programmed but
FPGA has not being configured after power is on.

What could be reasons for this, what I have missed?

Thank you.
From: Gabor on 18 Jun 2010 15:59
On Jun 18, 3:14 pm, Vic Orloff <vcorl...(a)gmail.com> wrote:
> Hello,
>
> I am a beginner and have tried to learn how to configure my FPGA
> (XC3S1600E) in Master Serial Mode using configuration of a design
> stored in Platform Flash PROM (XCF04S) .
> I use Xilinx ISE 9.1i and followed the steps described in 'Spartan-3
> Generation Configuration User Guide (ug332.pdf, pages 42-46 and
> 91-100) and everything seemed working alright - FPGA bitstream was
> generated, PROM file (.mcs) for Platform Flash PROM memory was created
> and PROM was successfuly programmed using JTAG ('Program Succeeded'
> message appeared). So everything seems working according to the guide
> but when I power board off and then on, my FPGA is not configured
> according to what I have programmed into PROM.
>
> So my problem is that although PROM is seemed correctly programmed but
> FPGA has not being configured after power is on.
>
> What could be reasons for this, what I have missed?
>
> Thank you.

You can get some debug information from Impact that will
tell you the state of the FPGA config pins. Make sure the
mode pins are correct for your device. Putting the whole
S3 series in one config guide is a bit confusing. The
mode pin definitions vary between S3 families.

Also make sure you generated the .bit file with CCLK as
the startup clock, and that you didn't increase the
CCLK frequency beyond the capability of the XCF04S.
Remember that CCLK frequencies can be +/- 50% of the
nominal value!

Check if the INIT line goes high then low again during startup.
This indicates a CRC error and could be caused by signal integrity
problems or if the .bit file is not generated properly, for example
with bits reversed.

If you have access to the PROG pin, try to ground it momentarily to
see if the FPGA will load. If it does, but not on power-up you may
have a power sequencing problem. If the supply that powers the
XCF04S is the last one up, the FPGA might try to start configuration
before the flash is ready.

It also helps to put a scope on the CCLK line. After power on is
it running constantly? This happens if the FPGA doesn't see a
proper bitstream startup sync pattern and keeps trying to shift in
data, as for example if the Flash is erased.

And of course double check the connections in the schematics for
master serial from the user guide. Make sure you have all the
necessary connections and pullup resistors.

HTH,
Gabor
From: Vic Orloff on 19 Jun 2010 16:57
On 19 июн, 11:43, Anssi Saari <a...(a)sci.fi> wrote:
> Vic Orloff <vcorl...(a)gmail.com> writes:
> > Hello,
>
> > I am a beginner and have tried to learn how to configure my FPGA
> > (XC3S1600E) in Master Serial Mode using configuration of a design
> > stored in Platform Flash PROM (XCF04S) .
>
> At the very least there's the slight problem of fitting almost 6 Mb of
> config data into a 4 Mb PROM. Presumably you used compression? But if
> so, did you limit CCLK to 20 MHz or below for configuration as
> described in the documentation?

Hello,

Yes, ConfigRate was set to 12 (which is approximately 12 MHz).
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