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From: JustJohn on 16 Jul 2010 20:03
On Jul 16, 3:01 pm, Tim Wescott <t...(a)seemywebsite.com> wrote:
> On 07/16/2010 02:24 PM, MM wrote:
>
>
>
>
>
> > "Tim Wescott"<t...(a)seemywebsite.com>  wrote in message
> >news:jKednaQFZYsOVN3RnZ2dnUVZ_jGdnZ2d(a)web-ster.com...
> >> I seem to have a collision between libraries in my Xilinx ISE:
>
> >> declaring both of the following:
>
> >> USE ieee.numeric_std.ALL;
> >> use IEEE.STD_LOGIC_ARITH.ALL;
>
> >> gets me a flood of errors, although I seem to be able to comment out the
> >> std_logic_arith.
>
> > These two libs should never be used together. The former is a standard
> > library, which should be used in new code, and the latter is a legacy
> > Synopsys library which might be required when working with the existing
> > code.
>
> Ah, Xilinx -- the latter is what Xilinx sticks in as boilerplate when
> you get lazy and tell it to just make you a test bench from a file.
>
> Thanks for the tip.
>
> --
>
> Tim Wescott
> Wescott Design Serviceshttp://www.wescottdesign.com
>
> Do you need to implement control loops in software?
> "Applied Control Theory for Embedded Systems" was written for you.
> See details athttp://www.wescottdesign.com/actfes/actfes.html- Hide quoted text -
>
> - Show quoted text -

It used to frustrate me no end the way ISE plugged in the wrong
library, until I found the script that does it and CHANGED it. Look
under Xilinx=>ISE=>data=>projnav=>scripts and modify file
"dpm_sourceTasks.tcl" to your liking. TCL syntax is fairly basic in
the area you'll want to change.
delete:
puts $hFile "use IEEE.STD_LOGIC_ARITH.ALL;"
puts $hFile "use IEEE.STD_LOGIC_UNSIGNED.ALL;"
add:
puts $hFile "use ieee.numeric_std.all;"

Customize to add your own name, company header, etc.
Hopefully they haven't changed the framework in version 12.

HTH,
John
From: Charles Gardiner on 17 Jul 2010 06:02
Hi Tim,

a good quick reference is the "Qualis Ref Card":
http://www.google.de/url?sa=t&source=web&cd=1&ved=0CBwQFjAA&url=http%3A%2F%2Fwww.vhdl.org%2Frassp%2Fvhdl%2Fguidelines%2Fvhdlqrc.pdf&rct=j&q=qualis%20vhdl%20refcard&ei=qX1BTIHIN9ecOODYraQN&usg=AFQjCNFjtNN-k9EA-H4S1K1CZrW58cNRrQ

or just type "qualis vhdl refcard" into the market hegemonial browser if the link
above is bent over 17 lines. It's the first hit (at leas it was for me)

Other references I use:
- VHDL Spec from IEEE
- Ashendon's Book

Or what I usually do, power up the Aldec activeHDL simulator (you can get a free
version from the Lattice website) and click on the Library manager. If you select
the IEEE libraries and go to the "Package Contents" window you get the prototypes
for all functions and procedures.

This might of course work in modelsim too, I haven't tried.

Regards,
Charles
From: Charles Gardiner on 17 Jul 2010 06:10
Hi again Tim,

sorry, the reference card you are probably really looking for is under

http://www.google.de/url?sa=t&source=web&cd=1&ved=0CBwQFjAA&url=http%3A%2F%2Fwww.vhdl.org%2Frassp%2Fvhdl%2Fguidelines%2F1164qrc.pdf&ei=_oBBTN7hKo2iOM6i7fAM&usg=AFQjCNHBm6d324gTZ40kvAWp6Lq0nB_5BQ

(or "qualis packages refcard" in the previously mentioned hegemonial search engine)

Charles
From: Jonathan Bromley on 17 Jul 2010 10:03
On Fri, 16 Jul 2010 14:06:00 -0700, Tim Wescott wrote:

>declaring both of the following:
>
>USE ieee.numeric_std.ALL;
>use IEEE.STD_LOGIC_ARITH.ALL;
>
>gets me a flood of errors, although I seem to be able to comment out the
>std_logic_arith.

Right. The two packages are somewhat similar. For example they
both define types SIGNED and UNSIGNED, and they both define "+"
operators for those types.

In VHDL, if you "use .all" some packages and more than
one of the packages defines the same identifier, then
the identifier is hidden to spare you the embarrassment
of not knowing which one is being used.

You can still reach it. For example, given your two
USE clauses, you could do

signal S8: SIGNED(7 downto 0); -- Error, SIGNED is hidden
signal S8: ieee.numeric_std.SIGNED(7 downto 0); -- OK

and, indeed,

S8 <= S8 + 1; -- ERROR: "+" operator definition is hidden
S8 <= ieee.numeric_std."+"(S8, 1); -- OK

but I suspect you would agree with me that neither of
these is a terribly good idea.

It's nice that JustJohn showed us how to defeat the silly
Xilinx default use clauses - thanks for the tip!
--
Jonathan Bromley
From: JustJohn on 17 Jul 2010 21:21
On Jul 16, 5:03 pm, JustJohn <justjohna...(a)gmail.com> wrote:
> On Jul 16, 3:01 pm, Tim Wescott <t...(a)seemywebsite.com> wrote:
>
>
>
>
>
> > On 07/16/2010 02:24 PM, MM wrote:
>
> > > "Tim Wescott"<t...(a)seemywebsite.com>  wrote in message
> > >news:jKednaQFZYsOVN3RnZ2dnUVZ_jGdnZ2d(a)web-ster.com...
> > >> I seem to have a collision between libraries in my Xilinx ISE:
>
> > >> declaring both of the following:
>
> > >> USE ieee.numeric_std.ALL;
> > >> use IEEE.STD_LOGIC_ARITH.ALL;
>
> > > These two libs should never be used together. The former is a standard
> > > library, which should be used in new code, and the latter is a legacy
> > > Synopsys library which might be required when working with the existing
> > > code.
>
> > Ah, Xilinx -- the latter is what Xilinx sticks in as boilerplate when
> > you get lazy and tell it to just make you a test bench from a file.
>
> > Thanks for the tip.
>
> > Tim Wescott
> > Wescott Design Serviceshttp://www.wescottdesign.com
>
> > Do you need to implement control loops in software?
> > "Applied Control Theory for Embedded Systems" was written for you.
> > See details athttp://www.wescottdesign.com/actfes/actfes.html-Hide quoted text -
>
> > - Show quoted text -
>
> It used to frustrate me no end the way ISE plugged in the wrong
> library, until I found the script that does it and CHANGED it. Look
> under Xilinx=>ISE=>data=>projnav=>scripts and modify file
> "dpm_sourceTasks.tcl" to your liking. TCL syntax is fairly basic in
> the area you'll want to change.
> delete:
>   puts $hFile "use IEEE.STD_LOGIC_ARITH.ALL;"
>   puts $hFile "use IEEE.STD_LOGIC_UNSIGNED.ALL;"
> add:
>   puts $hFile "use ieee.numeric_std.all;"
>
> Customize to add your own name, company header, etc.
> Hopefully they haven't changed the framework in version 12.
>
> HTH,
> John- Hide quoted text -
>
> - Show quoted text -

Umm, the tcl file I listed above is for regular vhdl modules. For
testbenches, the tcl'er is:
Xilinx->ver->ISE->data->testbnch2.tcl
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