Prev: Our customer websites are modern, fresh and accessible.
Next: Virtex 7?
From: Marc Jet on 31 May 2010 07:04
Hi,

The Spartan3 datasheet is very light on the topic of interconnect. I
wonder how big the effect of fanout is, on the delay of a route. I'm
not talking about "high fanout" signals like CLK, but rather just
normal logic signals.

For example, in a design I can choose to use fanout=5 (easy), or
fanout=4 (with extra cost somewhere else). The distance of the route
is about the same in both variants. Will fanout=4 significantly
improve the delay of the route?

For reference, "significant" for me would be ~0.3ns or more.

Thanks,
Marc
From: Chris Maryan on 31 May 2010 09:25
I don't have a complete answer to your question, but fanout delay is
generated primarily by switch boxes in Xilinx FPGAs. Switchboxes are
an integral part of routing and generating fanout, but I would guess
that for any reasonable design the dominant factor is the switchboxes
involved in routing switches, rather than those used to generate some
initial fanout on the output of a CLB. i.e. for a modest fanout, you
will go through one switchbox on the output to your CLB, but also
several more as your signal gets routed around the chip. I'd guess
this to be true for any signal that has sources and destinations that
aren't immediately adjacent to one another.

If you are really trying to squeeze an extra 300ps out of your design,
focus on pipelining and creating good area groups. If you really want
low delay routing, the switchbox next to each CLB is unaoidable unless
you find a way to use the carry chains, at which point your
destination has to be next to the source. Also, a large portion of the
fanout is generated along the routing, not immediately next to the
source, so it's hard to say exactly how fanout will be generated for
an arbitrary design. (i.e. it could be routed onto one line, then be
routed off that line at various points to other destinations, rather
than faning out at the source).

As an anecdotal data point, a high fanout net (~400 destinations) on a
V5 design I have handy show minimum delays of about 460ps and maximums
of around 9.7 ns. The key thing being that the 460ps destination is
right next to the source, while the 9.7ns destination is half way
across the chip. But this is a non-critical path for me, so I don't
care too much about max the delay.

For real insight into how all this works, find a mdeium-large design
and look at the routing in FPGA editor.

Chris
From: glen herrmannsfeldt on 31 May 2010 13:23
Chris Maryan <kmaryan(a)gmail.com> wrote:
> I don't have a complete answer to your question, but fanout delay is
> generated primarily by switch boxes in Xilinx FPGAs. Switchboxes are
> an integral part of routing and generating fanout, but I would guess
> that for any reasonable design the dominant factor is the switchboxes
> involved in routing switches, rather than those used to generate some
> initial fanout on the output of a CLB. i.e. for a modest fanout, you
> will go through one switchbox on the output to your CLB, but also
> several more as your signal gets routed around the chip. I'd guess
> this to be true for any signal that has sources and destinations that
> aren't immediately adjacent to one another.

As I understand it, most FPGAs now use internal buffers on long
routing lines. That is why no more true tristate nets. (The tools
will implement them using a MUX structure, so maybe you don't notice.)

Otherwise, for current CMOS, the load is more the capacitance of
the lines, and not so much the driven devices. More fanout will likely
result in more wire capacitance, but so will a single long route.

Down to about 0.8u CMOS could consider the lines as lumped capacitance,
but past that a distributed RC model is needed. But with buffers along
the way, the calculation is somewhat different.

-- glen
 | 
Pages: 1
Prev: Our customer websites are modern, fresh and accessible.
Next: Virtex 7?