Embedded clocks
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From: Jim Granville on 14 Aug 2006 15:51 rickman wrote: > Jim Granville wrote: > >> What we need is a CPLD like the Freescale RS08, or the SiLabs >>C8051F41x - that works from 1.8V to 5.5V, and draws 1uA static Icc :) >> [ ATF1502BE draws 2.3uA, but needs two rails.... ] > > > The Coolrunner XPLA3 parts are pretty good. Other than not having > schmitt trigger inputs, what don't you like about them? I like their JTAG enable pin, so you don't have to loose valuable pins for JTAG - but they are narrow Vcc operation, and only promise < 100uA, and Xilinx do not have them on the on-line store, and are sparse elsewhere, so have that NFND look about them.... How long is your product lifetime ? >>Two Pin A : Bidirectional pins ( see 4046 ) Open Collector, Res Pullups, >>Swings from GND to VthP, Nominally 50% duty cycle. Gates very well >>Can VCO modulate. > > > I don't get this one at all. I looked up the 4046 but all descriptions > I could find treat the VCO as a black box. I am guessing that the two > pins are driven with opposite polarity and the cap is grounded at one > end or the other all the time. So it would be charged like the one pin > approach and then discharged like the one pin approach. So this is a > pair of the one pin drivers to give you 50/50 duty cycle? > > This seems simple. Any issues with startup? Does it need FFs anywhere > to make it work without noise? I would think that the lack of schmitt > trigger inputs would require a FF. Yes, normally it is simply a SR latch, with some logic to catch S=R=H. When running, S,R cross their thresholds only briefly, to trigger the other phase. -jg
From: rickman on 14 Aug 2006 20:09 Jim Granville wrote: > rickman wrote: > > The Coolrunner XPLA3 parts are pretty good. Other than not having > > schmitt trigger inputs, what don't you like about them? > > I like their JTAG enable pin, so you don't have to loose valuable pins > for JTAG - but they are narrow Vcc operation, and only promise < 100uA, > and Xilinx do not have them on the on-line store, and are sparse > elsewhere, so have that NFND look about them.... > > How long is your product lifetime ? Xilinx still sells much older CPLDs and the XPLA3 parts are 5 volt tolerant which may not be in high demand in new designs, but you can't easily design the part out with a non-5 volt tolerant part in its place. I can buy them from stock at Digikey, so someone is still buying them. > >>Two Pin A : Bidirectional pins ( see 4046 ) Open Collector, Res Pullups, > >>Swings from GND to VthP, Nominally 50% duty cycle. Gates very well > >>Can VCO modulate. > > > > > > I don't get this one at all. I looked up the 4046 but all descriptions > > I could find treat the VCO as a black box. I am guessing that the two > > pins are driven with opposite polarity and the cap is grounded at one > > end or the other all the time. So it would be charged like the one pin > > approach and then discharged like the one pin approach. So this is a > > pair of the one pin drivers to give you 50/50 duty cycle? > > > > This seems simple. Any issues with startup? Does it need FFs anywhere > > to make it work without noise? I would think that the lack of schmitt > > trigger inputs would require a FF. > > Yes, normally it is simply a SR latch, with some logic to catch S=R=H. > When running, S,R cross their thresholds only briefly, to trigger the > other phase. Thanks for the tip. I think I will remember this circuit. It would appear to me that this circuit has more dependance on Vth and so would change frequency with temperature more than the three pin circuit which is supposed to be independant of Vth (of which I am not totally convinced). Peter's analysis of the three pin circuit looks pretty good. Any numbers available on the two pin circuit above?
From: Jim Granville on 14 Aug 2006 21:18 rickman wrote: >>>I don't get this one at all. I looked up the 4046 but all descriptions >>>I could find treat the VCO as a black box. I am guessing that the two >>>pins are driven with opposite polarity and the cap is grounded at one >>>end or the other all the time. So it would be charged like the one pin >>>approach and then discharged like the one pin approach. So this is a >>>pair of the one pin drivers to give you 50/50 duty cycle? >>> >>>This seems simple. Any issues with startup? Does it need FFs anywhere >>>to make it work without noise? I would think that the lack of schmitt >>>trigger inputs would require a FF. >> >>Yes, normally it is simply a SR latch, with some logic to catch S=R=H. >>When running, S,R cross their thresholds only briefly, to trigger the >>other phase. > > > Thanks for the tip. I think I will remember this circuit. It would > appear to me that this circuit has more dependance on Vth and so would > change frequency with temperature more than the three pin circuit which > is supposed to be independant of Vth (of which I am not totally > convinced). Peter's analysis of the three pin circuit looks pretty > good. Any numbers available on the two pin circuit above? Vth of CMOS does not change much with temperature, but the biggest variable, is the absolute value of Vth : that is a process variable. and being digital companies, FPGA vendors will not bother to band Vth as anything other than logic levels.... To check the dependance on Vth, simply drop any of these into spice :) On the 3 pin one, as Vth varies one half of the cycle lengthens, whilst the other half shortens - so the frequency is nominally compensated, but duty cycle varies. -jg
From: Brian Davis on 14 Aug 2006 22:09
rickman wrote: > >This could work and would only use two pins, one in each direction. >But the device itself would be pushing the boundary of what I would >like to use. > Your four pin scheme is a simpler solution if you have the pins, then you wouldn't need to find a small part with DLL/PLL. > >I assume I would need a 2x clock to generate the 90 degree skewing of >the trailing edge or even a 4x clock if I don't want to play tricks >with using opposite phases clocking FFs. > Yes; I'd probably try a 2x clock with DDR I/O for the transmit waveform. Symon wrote: > > Neat. I guess a problem could be that the signal has some data dependent DC > component. But 8B10B coding fixes that. > Right, that clock modulation scheme duplicates the DC balance of the transmit data; 8B10B should be a nice fit, giving both DC balance and a sync mechanism for alignment. Also, if you want to run near max cable/driver BW out & back, going to a 4x multiply at the "slave" instead of a 2x would make the narrowest modulated clock pulse width the same width as the bit period of the return data path, giving 1/4 rate outbound and 1x inbound data rates. Brian |