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From: Griffin on 16 Jun 2010 13:19
Hello,

I'm working on an embedded project (EDK 11.2) and am using the TEMAC
IP core (xps_ll_temac) and the TEMAC fifo (xps_ll_fifo).

From what I can tell, the size of the Tx fifo is only 2Kb; this causes
a bit of an issue for me: I am using my embedded project to stream 20
byte words over Ethernet. Right now, each packet contains a full IP
and UDP header, and 10 of these 20-byte words. This fills the FIFO in
its entirety.

The problem is that I recieve a new word every ~20 microseconds. Given
the size of the fifo, I'm firing off a packet every 200 microseconds.
This corresponds to a rate of about 5000 packets / second. The FPGA
can keep up with this data rate without issue, but it is too many
packets for the listening computer's software to handle, and the
entire system boggs down and crashes.

I am wondering if it is possible to increase the size of the FIFO
somehow, so that I could (say) include 100 20-byte words per packet
(ie, have a fifo that is ~16 Kb in size).

Does anyone know if what I want to do is possible? Are there any other
suggestions?

Thanks!

Sean Griffin
From: pbljung on 16 Jun 2010 14:48
On Jun 16, 10:19 am, Griffin <captain.grif...(a)gmail.com> wrote:
> I'm working on an embedded project (EDK 11.2) and am using the TEMAC
> IP core (xps_ll_temac) and the TEMAC fifo (xps_ll_fifo).
>
> I am wondering if it is possible to increase the size of the FIFO
> somehow, so that I could (say) include 100 20-byte words per packet
> (ie, have a fifo that is ~16 Kb in size).

We use xps_ll_temac and xps_ll_fifo when building +1GbE ethernet
stacks in hw. To support jumbo frames we replaced the hardwired 2kB
blockram FIFO with a VHDL version that supports parameterized depth
and width. The VHDL for the fifo is described at
www.codetronix.com/index.php?option=com_content&id=121

/Per
From: Griffin on 17 Jun 2010 19:29
Hi, thanks for the quick response!

I'll take a look as soon as I can (working on another experiment at
the moment) and get back to you, but at face value it seems to be what
it is I'm looking for.

-Sean.

> We use xps_ll_temac and xps_ll_fifo when building +1GbE ethernet
> stacks in hw. To support jumbo frames we replaced the hardwired 2kB
> blockram FIFO with a VHDL version that supports parameterized depth
> and width. The VHDL for the fifo is described atwww.codetronix.com/index.php?option=com_content&id=121
>
> /Per

From: Griffin on 18 Jun 2010 20:30
Is anyone else not able to view the link anymore? I can ping the site,
but not access the webpage.

-Sean.
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