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From: David on 29 Aug 2006 18:41
Thanks for your help guys, that fixed it. Interesting that the EDK
system assembly GUI doesn't hook up clock and reset by default...

Cheers,

David


Göran Bilski wrote:
> David wrote:
> > Göran Bilski wrote:
> >
> >
> >>David wrote:
> >>
> >>>Hi all,
> >>>
> >>>I'm trying to implement a correlator as a coprocessor on the FSL bus.
> >>>The first thing I've done is generate the FSL example using the create
> >>>peripheral wizard in EDK 8.1 and hooked it up to the MicroBlaze. When
> >>>I do a blocking write or read the MB stalls - my understanding is that
> >>>this will happen if the FSL FIFO is full or empty respectively, but it
> >>>happens the first time I write to it, so the FIFO should not be full.
> >>>
> >>>If I use non-blocking reads and writes and check the error and invalid
> >>>flags after each one using fsl_isinvalid() and fsl_iserror() - see code
> >>>below - everything seems normal but the output is always zero. Am I
> >>>implementing the error checking macros correctly?
> >>>
> >>>
> >>>#define write_into_fsl(val, id) nputfsl(val, id)
> >>>#define read_from_fsl(val, id) ngetfsl(val, id)
> >>>
> >>>#define WRITE_FSL_TEST_0(val) write_into_fsl(val,
> >>>XPAR_FSL_FSL_TEST_0_INPUT_SLOT_ID)
> >>>#define READ_FSL_TEST_0(val) read_from_fsl(val,
> >>>XPAR_FSL_FSL_TEST_0_OUTPUT_SLOT_ID)
> >>>
> >>>
> >>>void fsl_test_app(
> >>> unsigned int* input_0, /* Array size = 2 */
> >>> unsigned int* output_0 /* Array size = 2 */
> >>> )
> >>>{
> >>> int i;
> >>> Xuint8 is_error = 0;
> >>> Xuint8 is_valid = 0;
> >>>
> >>> print("Entering fsl_test_app \r\n");
> >>>
> >>> //Start writing into the FSL bus
> >>> for (i=0; i<2; i++)
> >>> {
> >>>
> >>> WRITE_FSL_TEST_0(input_0[i]);
> >>> fsl_iserror(is_error);
> >>> xil_printf("error post: %d \r\n", is_error);
> >>> fsl_isinvalid(is_valid);
> >>> xil_printf("valid post: %d \r\n", is_valid);
> >>> }
> >>> print("Finished Write \r\n");
> >>>
> >>> is_error = 0;
> >>> is_valid = 0;
> >>>
> >>> //Start reading from the FSL bus
> >>> for (i=0; i<2; i++)
> >>> {
> >>> READ_FSL_TEST_0(output_0[i]);
> >>> fsl_iserror(is_error);
> >>> xil_printf("error post: %d \r\n", is_error);
> >>> fsl_isinvalid(is_valid);
> >>> xil_printf("valid post: %d \r\n", is_valid);
> >>> }
> >>>}
> >>>
> >>>I added external ports to the FSL core to check the reset polarity and
> >>>monitor the state machine - the core is not being held at reset, but
> >>>always sits in the Idle state. This, coupled with the blocking
> >>>instruction problems seems to indicate an issue with the FSL FIFO
> >>>perhaps (I have tried both BRAM and non-BRAM FIFO implementations)?
> >>>If anyone has any ideas on what might be going wrong your help would be
> >>>much appreciated...
> >>>
> >>>
> >>>Cheers,
> >>>
> >>>David
> >>>
> >>
> >>Hi,
> >>
> >>Can you show the .mhs where you have connected your FSL core with
> >>Microblaze?
> >>
> >>Göran Bilski
> >
> >
> >
> > Hi Göran,
> >
> > Thanks for your reply, here are the relevant parts of the .mhs file:
> >
> > BEGIN microblaze
> > PARAMETER INSTANCE = microblaze_0
> > PARAMETER HW_VER = 4.00.a
> > PARAMETER C_USE_FPU = 0
> > PARAMETER C_DEBUG_ENABLED = 1
> > PARAMETER C_NUMBER_OF_PC_BRK = 2
> > PARAMETER C_FSL_LINKS = 1
> > BUS_INTERFACE DLMB = dlmb
> > BUS_INTERFACE ILMB = ilmb
> > BUS_INTERFACE DOPB = mb_opb
> > BUS_INTERFACE IOPB = mb_opb
> > BUS_INTERFACE SFSL0 = fsl_v20_0
> > BUS_INTERFACE MFSL0 = fsl_v20_1
> > PORT CLK = sys_clk_s
> > PORT DBG_CAPTURE = DBG_CAPTURE_s
> > PORT DBG_CLK = DBG_CLK_s
> > PORT DBG_REG_EN = DBG_REG_EN_s
> > PORT DBG_TDI = DBG_TDI_s
> > PORT DBG_TDO = DBG_TDO_s
> > PORT DBG_UPDATE = DBG_UPDATE_s
> > END
> >
> >
> > BEGIN fsl_v20
> > PARAMETER INSTANCE = fsl_v20_0
> > PARAMETER HW_VER = 2.00.a
> > PARAMETER C_EXT_RESET_HIGH = 0
> > PARAMETER C_IMPL_STYLE = 1
> > END
> >
> > BEGIN fsl_v20
> > PARAMETER INSTANCE = fsl_v20_1
> > PARAMETER HW_VER = 2.00.a
> > PARAMETER C_EXT_RESET_HIGH = 0
> > PARAMETER C_IMPL_STYLE = 1
> > END
> >
> > BEGIN fsl_test
> > PARAMETER INSTANCE = fsl_test_0
> > PARAMETER HW_VER = 1.00.c
> > BUS_INTERFACE MFSL = fsl_v20_0
> > BUS_INTERFACE SFSL = fsl_v20_1
> > PORT reset_out = fsl_test_0_reset_out
> > PORT state_debug = fsl_test_0_state_debug
> > END
> >
> > Cheers,
> >
> > David
> >
>
> Hi,
>
> You need to connect the system clock to the fsl_v20 modules.
> They are non clocked right now.
>
> One good trick is always to look at the top level vhdl file in the hdl
> directory. It's called system.vhd
>
> In that file you will see what signals are connected to what and it this
> case you should be able to see that the fsl bus doesn't have any clock
> connected.
>
> Göran Bilski

From: Felix Pang on 29 Aug 2006 23:49
Hi David,

It is decided by the MPD file of the IP. Refer to the MPD of FSL you should
see that the default connections of clock and reset are left blank.

-Feilx


"David" <simianfever(a)gmail.com> wrote in message
news:1156891272.252770.135520(a)b28g2000cwb.googlegroups.com...
Thanks for your help guys, that fixed it. Interesting that the EDK
system assembly GUI doesn't hook up clock and reset by default...

Cheers,

David


G?ran Bilski wrote:
> David wrote:
> > G?ran Bilski wrote:
> >
> >
> >>David wrote:
> >>
> >>>Hi all,
> >>>
> >>>I'm trying to implement a correlator as a coprocessor on the FSL bus.
> >>>The first thing I've done is generate the FSL example using the create
> >>>peripheral wizard in EDK 8.1 and hooked it up to the MicroBlaze. When
> >>>I do a blocking write or read the MB stalls - my understanding is that
> >>>this will happen if the FSL FIFO is full or empty respectively, but it
> >>>happens the first time I write to it, so the FIFO should not be full.
> >>>
> >>>If I use non-blocking reads and writes and check the error and invalid
> >>>flags after each one using fsl_isinvalid() and fsl_iserror() - see code
> >>>below - everything seems normal but the output is always zero. Am I
> >>>implementing the error checking macros correctly?
> >>>
> >>>
> >>>#define write_into_fsl(val, id) nputfsl(val, id)
> >>>#define read_from_fsl(val, id) ngetfsl(val, id)
> >>>
> >>>#define WRITE_FSL_TEST_0(val) write_into_fsl(val,
> >>>XPAR_FSL_FSL_TEST_0_INPUT_SLOT_ID)
> >>>#define READ_FSL_TEST_0(val) read_from_fsl(val,
> >>>XPAR_FSL_FSL_TEST_0_OUTPUT_SLOT_ID)
> >>>
> >>>
> >>>void fsl_test_app(
> >>> unsigned int* input_0, /* Array size = 2 */
> >>> unsigned int* output_0 /* Array size = 2 */
> >>> )
> >>>{
> >>> int i;
> >>> Xuint8 is_error = 0;
> >>> Xuint8 is_valid = 0;
> >>>
> >>> print("Entering fsl_test_app \r\n");
> >>>
> >>> //Start writing into the FSL bus
> >>> for (i=0; i<2; i++)
> >>> {
> >>>
> >>> WRITE_FSL_TEST_0(input_0[i]);
> >>> fsl_iserror(is_error);
> >>> xil_printf("error post: %d \r\n", is_error);
> >>> fsl_isinvalid(is_valid);
> >>> xil_printf("valid post: %d \r\n", is_valid);
> >>> }
> >>> print("Finished Write \r\n");
> >>>
> >>> is_error = 0;
> >>> is_valid = 0;
> >>>
> >>> //Start reading from the FSL bus
> >>> for (i=0; i<2; i++)
> >>> {
> >>> READ_FSL_TEST_0(output_0[i]);
> >>> fsl_iserror(is_error);
> >>> xil_printf("error post: %d \r\n", is_error);
> >>> fsl_isinvalid(is_valid);
> >>> xil_printf("valid post: %d \r\n", is_valid);
> >>> }
> >>>}
> >>>
> >>>I added external ports to the FSL core to check the reset polarity and
> >>>monitor the state machine - the core is not being held at reset, but
> >>>always sits in the Idle state. This, coupled with the blocking
> >>>instruction problems seems to indicate an issue with the FSL FIFO
> >>>perhaps (I have tried both BRAM and non-BRAM FIFO implementations)?
> >>>If anyone has any ideas on what might be going wrong your help would be
> >>>much appreciated...
> >>>
> >>>
> >>>Cheers,
> >>>
> >>>David
> >>>
> >>
> >>Hi,
> >>
> >>Can you show the .mhs where you have connected your FSL core with
> >>Microblaze?
> >>
> >>G?ran Bilski
> >
> >
> >
> > Hi G?ran,
> >
> > Thanks for your reply, here are the relevant parts of the .mhs file:
> >
> > BEGIN microblaze
> > PARAMETER INSTANCE = microblaze_0
> > PARAMETER HW_VER = 4.00.a
> > PARAMETER C_USE_FPU = 0
> > PARAMETER C_DEBUG_ENABLED = 1
> > PARAMETER C_NUMBER_OF_PC_BRK = 2
> > PARAMETER C_FSL_LINKS = 1
> > BUS_INTERFACE DLMB = dlmb
> > BUS_INTERFACE ILMB = ilmb
> > BUS_INTERFACE DOPB = mb_opb
> > BUS_INTERFACE IOPB = mb_opb
> > BUS_INTERFACE SFSL0 = fsl_v20_0
> > BUS_INTERFACE MFSL0 = fsl_v20_1
> > PORT CLK = sys_clk_s
> > PORT DBG_CAPTURE = DBG_CAPTURE_s
> > PORT DBG_CLK = DBG_CLK_s
> > PORT DBG_REG_EN = DBG_REG_EN_s
> > PORT DBG_TDI = DBG_TDI_s
> > PORT DBG_TDO = DBG_TDO_s
> > PORT DBG_UPDATE = DBG_UPDATE_s
> > END
> >
> >
> > BEGIN fsl_v20
> > PARAMETER INSTANCE = fsl_v20_0
> > PARAMETER HW_VER = 2.00.a
> > PARAMETER C_EXT_RESET_HIGH = 0
> > PARAMETER C_IMPL_STYLE = 1
> > END
> >
> > BEGIN fsl_v20
> > PARAMETER INSTANCE = fsl_v20_1
> > PARAMETER HW_VER = 2.00.a
> > PARAMETER C_EXT_RESET_HIGH = 0
> > PARAMETER C_IMPL_STYLE = 1
> > END
> >
> > BEGIN fsl_test
> > PARAMETER INSTANCE = fsl_test_0
> > PARAMETER HW_VER = 1.00.c
> > BUS_INTERFACE MFSL = fsl_v20_0
> > BUS_INTERFACE SFSL = fsl_v20_1
> > PORT reset_out = fsl_test_0_reset_out
> > PORT state_debug = fsl_test_0_state_debug
> > END
> >
> > Cheers,
> >
> > David
> >
>
> Hi,
>
> You need to connect the system clock to the fsl_v20 modules.
> They are non clocked right now.
>
> One good trick is always to look at the top level vhdl file in the hdl
> directory. It's called system.vhd
>
> In that file you will see what signals are connected to what and it this
> case you should be able to see that the fsl bus doesn't have any clock
> connected.
>
> G?ran Bilski


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