Filtering with Power of 2 Coefficients
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From: Darol Klawetter on 19 Feb 2010 11:24 I'm currently trying to pack more FIR filters into my FPGA. I'm up against the limit of available hardware multipliers so I'm going to attempt to convert some number of coefficients into values that are powers of 2 so that I can perform the multiplies with bit shifts. When I've done this before, I've used a trial and error approach until I converge on a solution. Is anyone aware of any filter software that will do this or maybe an analytic approach to finding the coefficients?
From: Eric Jacobsen on 19 Feb 2010 11:50 On 2/19/2010 9:24 AM, Darol Klawetter wrote: > I'm currently trying to pack more FIR filters into my FPGA. I'm up > against the limit of available hardware multipliers so I'm going to > attempt to convert some number of coefficients into values that are > powers of 2 so that I can perform the multiplies with bit shifts. When > I've done this before, I've used a trial and error approach until I > converge on a solution. Is anyone aware of any filter software that > will do this or maybe an analytic approach to finding the > coefficients? If you haven't already, search around for 'Canonic Signed Digit' implementation descriptions in the literature or on the web. There may be tools to do this, but some people get good results doing it manually. Having implementation experience helps here, to know where to get the best use of adders/subtractors, etc., and still get a good filter response. -- Eric Jacobsen Minister of Algorithms Abineau Communications http://www.abineau.com
From: Tim Wescott on 19 Feb 2010 11:51 On Fri, 19 Feb 2010 08:24:36 -0800, Darol Klawetter wrote: > I'm currently trying to pack more FIR filters into my FPGA. I'm up > against the limit of available hardware multipliers so I'm going to > attempt to convert some number of coefficients into values that are > powers of 2 so that I can perform the multiplies with bit shifts. When > I've done this before, I've used a trial and error approach until I > converge on a solution. Is anyone aware of any filter software that will > do this or maybe an analytic approach to finding the coefficients? I don't think you'll find an analytic approach. I don't know if there's software out there -- I suspect that any such effort will boil down to a brute-force search sooner or later. At best it'll be a constrained brute- force search. I do think it's worth seeing what you can do with just two bits per coefficient -- that gives you 2, 3, 5, 6, 7 (if you subtract in the ones place instead of add), 8, 9, 10, 12, etc. You need more additions per section, but may find that you're using fewer additions overall. You may also want to consider using IIR filters, if you can stand the phase distortion. IIR filters tend to use a lot fewer arithmetic resources for a given amount of filtering. Or multi-phase techniques -- do a bunch of coarse filtering with CIC filters, then do the detailed filtering at a lower sampling rate, possibly with one multiplier and a state machine to implement a FIR, instead of a bunch of multiply-adds all working in parallel. -- www.wescottdesign.com
From: dbd on 19 Feb 2010 12:28 On Feb 19, 8:24 am, Darol Klawetter <darol.klawet...(a)l-3com.com> wrote: > I'm currently trying to pack more FIR filters into my FPGA. I'm up > against the limit of available hardware multipliers so I'm going to > attempt to convert some number of coefficients into values that are > powers of 2 so that I can perform the multiplies with bit shifts. When > I've done this before, I've used a trial and error approach until I > converge on a solution. Is anyone aware of any filter software that > will do this or maybe an analytic approach to finding the > coefficients? A lot of people have approached this problem, often with solutions that are somewhat application specific. What kinds of filters do you need? Examples of 1 or few bits per coefficient filters include: D. J. Goodman, M. J. Carey, Nine digital filters for decimation and interpolation, IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-25, pp121-126, Apr. 1977 Search on: Hogenauer CIC filters A more complex example of very high performance requirement decomposed into filters with coefficients of 2 non-zero bits: Frequency-Response Masking Approach for the Synthesis of Sharp Linear Phase Digital Filters IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS VOL. CAS-33, NO. 4, APRIL 1986 p357 Available at: http://www-ee.uta.edu/online/oraintara/ee5350/pdfs/01085930.pdf Dale B. Dalrymple
From: Darol Klawetter on 19 Feb 2010 13:03
On Feb 19, 11:28 am, dbd <d...(a)ieee.org> wrote: > On Feb 19, 8:24 am, Darol Klawetter <darol.klawet...(a)l-3com.com> > wrote: > > > I'm currently trying to pack more FIR filters into my FPGA. I'm up > > against the limit of available hardware multipliers so I'm going to > > attempt to convert some number of coefficients into values that are > > powers of 2 so that I can perform the multiplies with bit shifts. When > > I've done this before, I've used a trial and error approach until I > > converge on a solution. Is anyone aware of any filter software that > > will do this or maybe an analytic approach to finding the > > coefficients? > > A lot of people have approached this problem, often with solutions > that are somewhat application specific. What kinds of filters do you > need? > > Examples of 1 or few bits per coefficient filters include: > > D. J. Goodman, M. J. Carey, Nine digital filters for decimation and > interpolation, IEEE Trans. Acoust., Speech, Signal Processing, vol. > ASSP-25, pp121-126, Apr. 1977 > > Search on: > Hogenauer CIC filters > > A more complex example of very high performance requirement decomposed > into filters with coefficients of 2 non-zero bits: > Frequency-Response Masking Approach > for the Synthesis of Sharp Linear Phase > Digital Filters > IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS VOL. CAS-33, NO. 4, APRIL > 1986 p357 > Available at:http://www-ee.uta.edu/online/oraintara/ee5350/pdfs/01085930.pdf > > Dale B. Dalrymple Thanks for the responses, everyone; I'll look into some of your suggestions. In my FPGA, which is being used to implement a 128 channel, independently tunable, sub-band receiver, I have some multi- channel polyphase, CIC, and half-band filters. Currently, I'm just trying to convert my half-band filters to power-of-2 coefficients. I need linear phase across each sub-band, so I haven't used any IIR filters, which I already have from other projects I've done. Darol Klawetter |